Apple_SANTANA-M51_PVT_051-7039_RevA.pdf

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8
7
6
5
4
3
REV
2
ZONE
ECN
DESCRIPTION OF CHANGE
1
CK
APPD
ENG
APPD
DATE
06/22/04
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
SANTANA - M51 MLB
PVT REV A - 08/04/06
MASTER DATE
M51_PAUL
M51_PAUL
M51_DAVE
08/04/2006
08/04/2006
(MASTER)
DATE
A
453469
PRODUCTION RELEASED
08/04/06
D
PDF CSA CONTENTS
TABLE_TABLEOFCONTENTS_HEAD
PDF CSA CONTENTS
TABLE_TABLEOFCONTENTS_HEAD
MASTER DATE
M51_DOUG
M51_DOUG
M51_DOUG
M51_DOUG
M51_DOUG
M51_DOUG
08/04/2006
08/04/2006
08/04/2006
08/04/2006
08/04/2006
Schematic / PCB #’s
TABLE_5_HEAD
D
CRITICAL
BOM OPTION
TABLE_5_ITEM
2
TABLE_TABLEOFCONTENTS_ITEM
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33
34
38
41
42
43
System Block Diagram
Power Block Diagram
BOM Config
FUNC TEST 1 OF 2
POWER CONN / MISC
CPU 1 OF 2-FSB
CPU 2 OF 2-PWR/GND
CPU DECAPS & VID<>
ASIC TEMP SENSORS
CPU ITP700FLEX DEBUG
NB CPU Interface
NB Misc Interfaces
NB DDR2 Interfaces
NB Power 1
NB Power 2
NB Grounds
NB (GM) Decoupling
NB Config Straps
SB: 1 OF 4
SB: 2 OF 4
SB: 3 OF 4
SB: 4 OF 4
SB:DECOUPLING
SB: MISC
M51 SMBus Connections
38
TABLE_TABLEOFCONTENTS_ITEM
44
45
46
47
53
54
58
59
60
63
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
82
83
84
85
94
97
FW: 1394B-LINK/PHY
FW: 1394B MISC
FIREWIRE CONNECTORS
USB Device Interfaces
AIRPORT CONN
PCI-E CONNECTIONS
SMC
SMC & TPM SUPPORT
LPC+ CONN
SPI BOOTROM
HD AND OD FAN
CPU FAN, HD & OD TEMP
TPM
AUDIO: CODEC
AUDIO: LINE INPUT AMP
AUDIO: COMBO OUT AMP
AUDIO: SPEAKER AMP_1
AUDIO: SPEAKER AMP
AUDIO: CONNECTORS
PART#
051-7039
820-1984
QTY
1
1
DESCRIPTION
PCB,SCHEM,MLB,M51
PCB,FAB,MLB,M51
REFERENCE DESIGNATOR(S)
SCH1
MLB1
3
TABLE_TABLEOFCONTENTS_ITEM
39
TABLE_TABLEOFCONTENTS_ITEM
4
TABLE_TABLEOFCONTENTS_ITEM
40
TABLE_TABLEOFCONTENTS_ITEM
5
TABLE_TABLEOFCONTENTS_ITEM
M51_HENRY 08/04/2006
M51_PAUL
08/04/2006
41
TABLE_TABLEOFCONTENTS_ITEM
6
TABLE_TABLEOFCONTENTS_ITEM
42
TABLE_TABLEOFCONTENTS_ITEM
7
TABLE_TABLEOFCONTENTS_ITEM
M50_HENRY 08/04/2006
M50_HENRY 08/04/2006
M51_HENRY 08/04/2006
M51_DAVE
(MASTER)
43
TABLE_TABLEOFCONTENTS_ITEM
8
TABLE_TABLEOFCONTENTS_ITEM
44
TABLE_TABLEOFCONTENTS_ITEM
M51_HENRY 08/04/2006
M51_HENRY 07/31/2006
M51_HENRY 08/04/2006
M50_DOUG
08/04/2006
9
TABLE_TABLEOFCONTENTS_ITEM
45
TABLE_TABLEOFCONTENTS_ITEM
10
TABLE_TABLEOFCONTENTS_ITEM
46
TABLE_TABLEOFCONTENTS_ITEM
11
TABLE_TABLEOFCONTENTS_ITEM
M50_HENRY 08/04/2006
M50_HENRY 08/04/2006
08/04/2006
47
TABLE_TABLEOFCONTENTS_ITEM
C
12
TABLE_TABLEOFCONTENTS_ITEM
48
TABLE_TABLEOFCONTENTS_ITEM
M51_HENRY 08/04/2006
M51_HENRY 08/04/2006
M51_HENRY 08/04/2006
13
TABLE_TABLEOFCONTENTS_ITEM
NB PEG / Video Interfaces
M50_HENRY
49
TABLE_TABLEOFCONTENTS_ITEM
14
TABLE_TABLEOFCONTENTS_ITEM
M50_HENRY 08/04/2006
M50_HENRY 08/04/2006
M51_HENRY 08/04/2006
M51_HENRY 08/04/2006
M50_HENRY 08/04/2006
M51_DAVE
(MASTER)
50
TABLE_TABLEOFCONTENTS_ITEM
15
TABLE_TABLEOFCONTENTS_ITEM
51
TABLE_TABLEOFCONTENTS_ITEM
16
TABLE_TABLEOFCONTENTS_ITEM
52
TABLE_TABLEOFCONTENTS_ITEM
17
TABLE_TABLEOFCONTENTS_ITEM
53
TABLE_TABLEOFCONTENTS_ITEM
18
TABLE_TABLEOFCONTENTS_ITEM
54
TABLE_TABLEOFCONTENTS_ITEM
19
TABLE_TABLEOFCONTENTS_ITEM
55
TABLE_TABLEOFCONTENTS_ITEM
20
TABLE_TABLEOFCONTENTS_ITEM
M50_HENRY 08/04/2006
M50_DOUG
M51_DOUG
M51_DOUG
M50_DOUG
M51_DOUG
M50_DOUG
M51_DAVE
08/04/2006
08/04/2006
08/04/2006
08/04/2006
08/04/2006
08/04/2006
(MASTER)
56
TABLE_TABLEOFCONTENTS_ITEM
21
TABLE_TABLEOFCONTENTS_ITEM
B
22
TABLE_TABLEOFCONTENTS_ITEM
23
TABLE_TABLEOFCONTENTS_ITEM
24
TABLE_TABLEOFCONTENTS_ITEM
25
TABLE_TABLEOFCONTENTS_ITEM
26
TABLE_TABLEOFCONTENTS_ITEM
27
TABLE_TABLEOFCONTENTS_ITEM
28
TABLE_TABLEOFCONTENTS_ITEM
DDR2 SO-DIMM Connector A
M51_HENRY
DDR2 SO-DIMM Connector B
M51_HENRY
Memory Active Termination
M50_HENRY
Memory Vtt Supply
CLOCKS
CLOCKS:
TERMINATIONS
Disk Connectors
ETHERNET CONTROLLER
ETHERNET MISC
ETHERNET CONNECTOR
29
TABLE_TABLEOFCONTENTS_ITEM
30
TABLE_TABLEOFCONTENTS_ITEM
31
TABLE_TABLEOFCONTENTS_ITEM
M50_HENRY 08/04/2006
M50_HENRY 08/04/2006
M51_HENRY 08/04/2006
M51_DOUG
M50_DOUG
M51_DOUG
M51_DOUG
08/04/2006
08/04/2006
08/04/2006
08/04/2006
32
A
TABLE_TABLEOFCONTENTS_ITEM
33
TABLE_TABLEOFCONTENTS_ITEM
P
08/04/2006
08/04/2006
08/04/2006
e
r
57
58
59
60
61
62
63
64
65
66
67
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
AUDIO: POWER SUPPLIES
CPU & SYSTEM SENSE
PWR GOOD
3V DC/DC 2.5V
IMVP6 CPU VCore Regulator
M51_PAUL
M51_DAVE
M51_PAUL
M51_PAUL
M51_PAUL
M51_PAUL
M51_PAUL
M51_PAUL
M51_DAVE
M51_DAVE
M51_DAVE
M51_DAVE
1.8V & 1.2V VREG
5V DC/DC
S0 AND S3 FETS
MXM PCI-E & PWR
MXM I/O
m
i
l
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
a
n
i
08/04/2006
08/04/2006
08/04/2006
08/04/2006
08/04/2006
08/04/2006
08/04/2006
08/04/2006
08/04/2006
(MASTER)
08/04/2006
08/04/2006
08/04/2006
08/04/2006
08/04/2006
08/04/2006
(MASTER)
(MASTER)
(MASTER)
(MASTER)
X.XXX
ANGLES
DIMENSIONS ARE IN MILLIMETERS
XX
X.XX
DO NOT SCALE DRAWING
THIRD ANGLE PROJECTION
y
r
METRIC
DESIGN CK
MFG APPD
TABLE_5_ITEM
C
B
1.5V_S0 & 1.05V_S0 VREG
Apple Computer Inc.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
68
TABLE_TABLEOFCONTENTS_ITEM
Internal Display Conns
External Display Conns
69
TABLE_TABLEOFCONTENTS_ITEM
DRAFTER
A
34
TABLE_TABLEOFCONTENTS_ITEM
ENG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
QA APPD
DESIGNER
TITLE
35
TABLE_TABLEOFCONTENTS_ITEM
36
TABLE_TABLEOFCONTENTS_ITEM
RELEASE
SCALE
NONE
SIZE
SCHEM SANTANA
DRAWING NUMBER
37
TABLE_TABLEOFCONTENTS_ITEM
MATERIAL/FINISH
NOTED AS
APPLICABLE
D
051-7039
SHT
REV.
A
OF
97
1
8
7
6
5
4
3
2
1
8
7
6
J0700
5
CPU
PAGE 7
J1101
(1.83/2.17GHZ)
CORE (~1.2V)
PAGE 8
4
ITP
CONN
PAGE 11
3
2
1
J9700
J9402
MINI-DVI
(TMDS - VGA)
LVDS
(INTERNAL)
PAGE 94
64-BIT
FSB
667MHZ
D
PAGE 97
D
J2800
J2900
MAIN MEMORY
PAGE 12
PCI-E
PAGE
13
NB- GM
CORE (1.05V)
PAGE 16-17
PAGE 15
U1200
DDR2 - DUAL CHAN
1.8V/667MHZ
64-BIT
DIMM
PARALLEL
TERM
PAGES 30
PAGE 28-29
MISC
PAGE 14
DMI
PAGE 14
J8400
J2901 ALS+AMBIENT TSENS P. 59
4-BIT
DMI
1.2V/800MHZ
TEMP SENSE
SEE I2C PG 27
MXM CONNECTOR
PAGES 84-85
CONTROL = 2.5V
POWER SENSE
C
U6300/01
SEE POWER BLOCK DIAGRAM
PG 3
SPI
BOOTROM
PAGE 63
A
B,0 ADC FAN
SMB
J6500,J6501,J6600 FAN CONNS
JC900
LPC
DMI
SPI
PAGE 21
SATA
CONNECTOR
HARD DRIVE
PAGE 38
JC901
3.3V/133MHZ
OPTICAL
PAGE 38
B
X1 - 1.5GHZ
X1 - 1.5GHZ
J5300
U4101
MINI-PCIE
AIRPORT
YUKON
PAGE 41
GIG ETHERNET
A
PAGE 53
4 Diff pairs
JD600
P
e
r
TSB82AA2
FIREWIRE B
PAGE 44
6
5
3,7
CORE (1.05V)
USB
UATA/133
PAGE 22
UATA
CONNECTOR
SB
J5300 (AIRPORT CONN)
IR
U2100
1 0,2,4
CAMERA
1.2V/1.5GHZ
PAGE 22
CORE
GPIOS
PAGE 23
PCI
AZALIA
PAGE 22
PAGE 21
PAGE 27
PAGE 24
33MHZ
32-BIT
m
i
l
TPM
PAGE 58
PAGE 67
PAGE 22
SMC
U5800
U6700
4-BIT (3.3V/33MHZ)
a
n
i
U3301
CK410
CLOCKS
PAGE 33
TERMS
PAGE 34
y
r
JE351
J4700
6DUAL CHANNEL LVDS - 6BIT
C
J6000
LPC+ CONN
PAGE 60
JE310/JE320/JE330
JE350
USB
CONNECTORS
0
2
4
CAMERA
PAGE 47
3
IR RCV
PAGE 47
7
BT
CONN
PAGE 48
SMB
TSB81BA3
PORT F
PAGE 21
SATA2
SATA0
PAGE 21
PORT
#2-5
PORT
#0
PAGE 47
FIREWIRE B
PAGE 45
0
1
2
OPTICAL IN
J7303
SATA
UATA
PCI-E
B
PAGE 22
PORT
#1
J2800
J2900
DIMM’S
U3301
J5300
CK410M
AIRPORT
U6800
100MHZ
8-BIT
S/PDIF
AUDIO CODEC
STA9221
PAGE 68
PORT A
PORT C
PORT B
OPTICAL OUT
J7303
COMBO OUT
CONNECTOR
PAGE 73
LINE OUT
System Block Diagram
SYNC_MASTER=M51_PAUL
SYNC_DATE=08/04/2006
NOTICE OF PROPRIETARY PROPERTY
J7301,J7302
A
SPEAKER
AMP
PAGE 72
JE350
MIC IN
BNDI
INTERFACE
R/L
SPEAKER
CONNECTORS
PAGE 73
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
REV.
ETHERNET
CONNECTOR
PAGE 43
2 Diff pairs
JE000, JE001
FIREWIRE B
CONNECTORS
PAGE 46
COMBO IN
CONNECTOR
PAGE 73
LINE IN
APPLE COMPUTER INC.
D
SCALE
NONE
051-7039
SHT
A
97
2
OF
8
7
6
5
4
3
2
1
8
7
6
230W AC/DC POWER SUPPLY
12V, ?A
S5
5
24V, ?A
S5
4
3
2
1
SYSTEM (12V)
ISENSE AND VSENSE
U7650
D
12V, 14.5A PK [9.4A AVG]
SWITCHER
PAGE 82
5V, 3.4A PK [2.2A AVG]
SWITCHER
PAGE 78
3.3V, 7.1A PK [4.1A AVG]
24V, 3.7A PK [3.3A AVG]
D
83
80
PP12V_S5
78
76
7.4A PEAK
5.5A AVG
AC/DC BOARD
MAKE_BASE=TRUE
VOLTAGE=12V
MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
77
79
82
PP12V_S0
?A PEAK
?A AVG
FET PG 83
?A PEAK
?A AVG
FET PG 83
MAKE_BASE=TRUE
VOLTAGE=12V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.15MM
83
PP5V_S5
1.7A PEAK
1.7A AVG
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
80
78
75
5
59
77
79
82
83
PP5V_S0
3.4A PEAK
2.2A AVG
FET PG 83
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
97
75
5
59
83
PP3V3_S5
1.1A PEAK
0.9A AVG
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
5 6 26 65 66 76 77 78 79 80 83
PP12V_S0_B
MAKE_BASE=TRUE
VOLTAGE=12V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.15MM
6.0A PEAK
3.4A AVG
FET PG 83
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
76
83
XW301
SM
1
SM
1
72 71
OMIT
2
PP12V_S5_AUDIO_SPKRAMP
MAKE_BASE=TRUE
XW302
=PP12V_S0_SATA
=PPV_S0_LCD
=PP5V_S5_SB
=PP5V_S5_AUDIO_LDO
6
94
25
82
ODD
=PP5V_S0_SB
=PP5V_S0_PATA
=PP5V_S0_DEBUG
=PP5V_S0_SATA
=PP5V_S0_MXM
=PP5V_S0_AUDIO
25
38
OMIT
2
60
6
84
70
PP4V5_S5_AUDIO_ANALOG
MAKE_BASE=TRUE
VOLTAGE=4.5V
82
HDD
=PP12V_S5_AUDIO_SPKRAMP
?A PEAK
MIN_LINE_WIDTH=0.6MM
?A AVG
MIN_NECK_WIDTH=0.25MM
LINEAR PG 82
=PP4V5_S5_AUDIO_ANALOG
PP1V8_S3
14.5A PEAK
6.3A AVG
SWITCHER
PAGE 79
MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
83
5
79
68
=PP12V_S0_FAN
=PPV_S0_MXM_PWRSRC
MXM_PWRSRC (12V)
ISENSE + VSENSE
U8450
65 66
=PP3V3_S5_SB
23 25 26
=PP3V3_S5_SB_USB
22
=PP3V3_S5_SB_PM
11 23
=PP3V3_S5_SB_VCCSUS3_3
24 25
=PP3V3_S5_SB_VCCSUS3_3_USB
24 25
=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA
24
=PP3V3_S5_SB_IO
22
=PP3V3_S5_FW
44 45 46
=PP3V3_S5_SMC
27 58 59
=PP3V3_S5_2V5_LDO
78
=PP3V3_S5_DEBUG
60
=PP3V3_S5_ROM
63
84
PP5V_S3
1.5A PEAK
1.5A AVG
FET PG 83
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
59
83
C
=PP1V8_S3_MEM_NB
=PP1V8_S3_MEM
=PP1V8_S3_1V2_LDO
=PP1V8_S0_MEMVTT
14 16 19
28 29
79
31
PP1V8_S0
3.5A PEAK
1.2A AVG
FET PG 83
MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.15MM
=PP5V_S3_USB
=PP5V_S3_BNDI
=PP5V_S0_MEMVTT
83
47
47
31
0.2A PEAK
0.2A AVG
FET PG 83
=PP1V8_S0_MXM
84
PP0V9_S0
1.0A PEAK
0.4A AVG
LINEAR
PAGE 31
MAKE_BASE=TRUE
VOLTAGE=0.9V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
79
=PP0V9_S0_MEMVTT_LDO
=PP0V9_S0_MEM_TERM
31
29 30
PP1V5_S0
5.8A PEAK
2.4A AVG
SWITCHER
PAGE 80
MAKE_BASE=TRUE
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
5 80
B
=PP1V5_S0_CPU
8
=PP1V5_S0_NB_PCIE
13
=PP1V5_S0_NB_TVDAC
19
=PP1V5_S0_NB_VCCD_HMPLL
17
=PP1V5_S0_NB_VCCAUX
16 17 19
=PP1V5_S0_NB_PLL
19
=PP1V5_S0_NB
19
=PP1V5_S0_NB_3GPLL
19
=PP1V5_S0_SB_VCC1_5_A_ARX
24 25
=PP1V5_S0_SB_VCCSATAPLL
24 25
=PP1V5_S0_SB_VCC1_5_A_ATX
24 25
=PP1V5_S0_SB_VCCUSBPLL
24 25
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
24 25
=PP1V5_S0_SB_VCC1_5_A
24 25
=PP1V5_S0_SB
25
=PP1V5_S0_AIRPORT
53
1UH-20A-4.5MOHM
1
TH-VERT-LF
2
75
L300
PP12V_S5_CPU_REG
VOLTAGE=12V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
PPVCORE_CPU
36A PEAK
34A AVG
SWITCHER
PAGE 75
MAKE_BASE=TRUE
VOLTAGE=1.25V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.15MM
A
PP1V05_S0
8.4A PEAK
4.5A AVG
SWITCHER
PAGE 81
MAKE_BASE=TRUE
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
80
5
34
=PPVCORE_S0_CPU
P
76
5
75
8 9 76
e
r
"S0" RAILS
ONLY ON IN RUN
m
i
l
5
4
0.4A PEAK
0.3A AVG
LINEAR
PAGE 79
a
n
i
PP3V3_S3
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
53
6
27
83
=PP3V3_S0_SATA
=PP3V3_S0_MXM
=PP3V3_S0_NB_VCC_HV
=PP3V3_S0_SB
=PP3V3_S0_SB_GPIO
=PP3V3_S0_SB_VCC3_3
=PP3V3_S0_SB_VCC3_3_PCI
=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S0_SB_PCI
=PP3V3_S0_SB_PM
=PP3V3_S0_PATA
=PP3V3_S0_FAN
=PP3V3_S0_HD_TSENS
=PP3V3_S0_ODD_TSENS
=PP3V3_S0_SB_3V3_1V5_VCCHDA
=PP3V3_S0_TPM
=PPSPD_S0_MEM
=PP3V3_S0_CK410
=PP3V3_S0_IMVP
=PP3V3_S0_AUDIO
=PP3V3_S0_SB_VCCLAN3_3
=PP3V3_S0_AIRPORT
=PP3V3_S0_NB
=PP3V3_S0_VIDEO
y
r
PP3V3_S0
83
5 6 10 26 27 41 45
76
84
PP24V_S5
6 83
PP24V_S0
3.3A PEAK
3.0A AVG
FET PG ?
MAKE_BASE=TRUE
VOLTAGE=24V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
5 83
0.4A PEAK
0.3A AVG
AC/DC
MAKE_BASE=TRUE
VOLTAGE=24V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
=PPV_S5_FW
46
=PPV_S0_INVERTER
94
6
85
17 19
22 25
21 23 27
24 25
24 25
24 25
26
26
38
59 65 66
66
66
24 25
67
C
28 29
33 34
75
68 71 72 73 74
24 25
53
14 20
94 97
=PP3V3_S3_ENET
=PP3V3_S3_TPM
=PP3V3_S3_BT
=PP3V3_S3_I2C
=PP3V3_S3_FW
41 42 43
67
47
47
44 45
PP1V2_S3
MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
5
79
=PP1V2_S3_LAN
42
PP1V95_S5
MAKE_BASE=TRUE
VOLTAGE=1.95V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
45
0.1A PEAK
0.1A AVG
LINEAR
PAGE 45
B
44 45
=PP1V95_S5_FWPHY
0.6A PEAK
0.2A AVG
LINEAR
PAGE 78
MAKE_BASE=TRUE
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
PP2V5_S5
OUT
83
5
78
PP2V5_S0
0.6A PEAK
0.2A AVG
LINEAR
PAGE 83
MAKE_BASE=TRUE
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
78
83
GRAPHICS
=PP2V5_S0_MXM
85
=PP2V5_S0_NB_VCCA_3GBG
17
19
Power Block Diagram
SYNC_MASTER=M51_PAUL
SYNC_DATE=08/04/2006
"S3" RAILS
ON IN RUN AND SLEEP
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
A
CPU VCORE (1.25V)
ISENSE AND VSENSE
U7600
"S5" RAILS
ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)
7 8 9 11
12
17 19
21 24 25
24 25
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
REV.
=PP1V05_S0_CPU
=PP1V05_S0_FSB_NB
=PP1V05_S0_NB_VTT
=PP1V05_S0_SB_CPU_IO
=PPVCORE_S0_SB
=PPVCORE_S0_NB
APPLE COMPUTER INC.
D
SCALE
NONE
051-7039
SHT
A
97
16 19
3
OF
8
7
6
3
2
1
8
Production BOM
7
6
5
4
3
2
1
TABLE_BOMGROUP_HEAD
BOM NUMBER
630-7512
630-7595
BOM NAME
PCBA,MLB,2.33GHz,M51
PCBA,MLB,2.16GHz,M51
BOM OPTIONS
TABLE_BOMGROUP_ITEM
M51_COMMON,M51_BEST,EEE_V4K,PRODUCTION
TABLE_BOMGROUP_ITEM
Alternate Parts
TABLE_ALT_HEAD
M51_COMMON,M51_BETTER,EEE_VMD,PRODUCTION
PART NUMBER
ALTERNATE FOR
PART NUMBER
126S0078
126S0073
126S0088
124-0339
BOM OPTION
REF DES
COMMENTS:
126S0086
TABLE_BOMGROUP_HEAD
D
Development BOM
BOM NUMBER
603-8960
BOM NAME
PCBA,DEVBOM,M51
BOM OPTIONS
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
ALL
ALL
ALL
ALL
Sanyo alt for Nich.
TABLE_ALT_ITEM
126S0099
126S0068
124-0361
Sanyo alt for Nich.
TABLE_ALT_ITEM
D
M51_DEVELOPMENT
BOMOPTION Groups
TABLE_BOMGROUP_HEAD
BOM GROUP
M51_COMMON
M51_COMMON1
M51_COMMON2
M51_DEVELOPMENT
M51_DEV1
BOM OPTIONS
TABLE_BOMGROUP_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
378S0140
353S1465
740S0028
BOM OPTION
COMMON,M51_COMMON1,M51_COMMON2,ALTERNATE
TABLE_BOMGROUP_ITEM
378S0141
353S1461
TABLE_BOMGROUP_ITEM
CPU_TSENS_EXT,GPU_TSENS_INT,GPU_TSENS_EXT,MXM_ROM,NBCFG_PEG_REVERSE
SB_SYSRST_4_PVT,ITP,MEROM,AMB_TSENS,CPU_PWR_SENSE,MXM_PWR_SENSE
TABLE_BOMGROUP_ITEM
740S0044
DEVELOPMENT,M51_DEV1
TABLE_BOMGROUP_ITEM
CPU_TSENS_INT,SYS_PWR_SENSE
MEROM BOM OPTION DUE TO PAGE 76 SHARING W/ M50
BarCode Label / EEE #’s
PART NUMBER
825-6447
825-6447
QTY
1
1
DESCRIPTION
BAR CODE LABLE, MLB, M51
BAR CODE LABLE, MLB, M51
REFERENCE DES
[EEE:VMD]
[EEE:V4K]
CRITICAL
CRITICAL
CRITICAL
BOM OPTION
EEE_VMD
EEE_V4K
C
CHIPSET, ROMS, ETC.
PART NUMBER
511S0025
338S0328
343S0385
359S0117
338S0270
(335S0382)
SENSOR STUFFING OPTIONS
REFERENCE DES
J0700
U1200
U2100
U3301
U4101
U4102
U6700
U7500
U8570
U6301
U5800
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
MXM_ROM
TPM
BOM OPTION
PART#
102S0699
116S0090
116S0090
QTY
1
1
1
DESCRIPTION
RES,0-OHM,2010
RES,10K-OHM,5%,0402
RES,10K-OHM,5%,0402
QTY
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
IC,CPU-SKT,479BGA
IC,945PM,NORTHBRIDGE
IC,SB,652BGA
IC,SLG84435,CLK GEN,68PIN QFN
IC,88E8053,GIGABIT ENET XCVR,64P QFN,NO
MUST STUFF WHEN SYS_PWR_SENSE IS NOT STUFFED (I.E. WHEN DEVELOPMENT BOM IS NOT STUFFED)
TABLE_5_HEAD
341S1797
341S1789
353S1465
341S1892
341T0019
341T0020
IC,ENET LAN ROM
IC,TPM,TSSOP,28P
IC,CPU VREG,IMVP,TWO PHASE,SCREENED
IC,2K I2C EEPROM,MXM,M51
IC,EFI BOOT ROM,M51
IC,SMC,M51
(335S0384)
(338S0274)
PROCESSORS
B
PART NUMBER
337S3392
337S3390
QTY
1
1
DESCRIPTION
MEROM 2.33GHZ, M51
MEROM 2.16GHZ, M51
REFERENCE DES
CPU
CPU
CRITICAL
CRITICAL
CRITICAL
Misc. Parts
PART NUMBER
742-0048
820-2038
946-0743
378S0193
QTY
1
1
1
1
DESCRIPTION
BAT,COIN,3V,220MAH,CR2032
IO ALIGNMENT BOARD, M51
IO ALIGNMENT BOARD ADHESIVE
LED,WHITE,740MCD,LF,3X2MM
REFERENCE DES
BT2600
PCB2
ADH1
LED5950
A
P
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
e
r
BOM OPTION
M51_BEST
M51_BETTER
BOM OPTION
NOSTUFF
m
i
l
PART#
QTY
1
1
1
DESCRIPTION
107S0070
116S0090
116S0090
RES,0-OHM,2512
RES,10K-OHM,5%,0402
RES,10K-OHM,5%,0402
PART#
QTY
1
1
DESCRIPTION
116S0090
116S0090
RES,10K-OHM,5%,0402
RES,10K-OHM,5%,0402
MUST STUFF WHEN MXM_PWR_SENSE IS NOT STUFFED (IF THIS MOVES TO DEV BOM)
REFERENCE DESIGNATOR(S)
R8450
C8458
C8459
a
n
i
REFERENCE DESIGNATOR(S)
R7650
C7650
C7650
BOM OPTION
PRODUCTION
PRODUCTION
PRODUCTION
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
y
r
Sanyo alt for Nich.
SANYO ALT
TABLE_ALT_ITEM
TABLE_ALT_HEAD
REF DES
COMMENTS:
TABLE_ALT_ITEM
ALL
GREEN LED ALT.
TABLE_ALT_ITEM
U7500
F9710
CPU VREG NEW REV
TABLE_ALT_ITEM
DVI DDC (LITTLEFUSE)
C
PULL-DOWNS FOR UNUSED PINS
WHEN DEVELOPMENT SENSORS ARE GONE
BOM OPTION
NOSTUFF
NOSTUFF
NOSTUFF
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PULL-DOWNS FOR UNUSED PINS
WHEN DEVELOPMENT SENSORS ARE GONE
MUST STUFF WHEN CPU_PWR_SENSE IS NOT STUFFED (IF THIS MOVES TO DEV BOM)
TABLE_5_HEAD
REFERENCE DESIGNATOR(S)
C7602
C7612
BOM OPTION
TABLE_5_ITEM
NOSTUFF
TABLE_5_ITEM
NOSTUFF
PULL-DOWNS FOR UNUSED PINS
WHEN DEVELOPMENT SENSORS ARE GONE
B
BATTERY IS INSTALLED AT FATP
BOM Config
SYNC_MASTER=M51_DAVE
SYNC_DATE=(MASTER)
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
REV.
A
APPLE COMPUTER INC.
D
SCALE
NONE
051-7039
SHT
A
97
4
OF
8
7
6
5
4
3
2
1
8
LAYOUT:
PLACE CLOSE TO DESTINATION
* OPPOSITE END FROM CLOCK BUFFER
7
FSB SIGNALS
12 11 7
6
I473
1
SM PP
14
5
NB_CFG<17>
I474
14
4
76 75 3
80 79 78 77 76 66 65 26 6 5 3
83
3
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
83 78 3
83 79 3
79 3
80 3
80 34 3
83 82 80 79 78 77 75 59 5 3
97 83 75 59 3
83 82 80 79 78 77 75 59 5 3
80 79 78 77 76 66 65 26 6 5 3
83
84 83 76 45 41 27 26 10 6 3
83 3
2
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
11 7
11 7
11 7
11 7
26 11 7
26 5
59 5
67 60 58 21
67 60 58 21
67 60 58 21
67 60 58 21
67 60 58 21 5
67 60 58 23
60 58 22
1
60 59 58
60 59 58
60 59 58
60 59 58
60 58
FSB_CPURST_L
PP621
NC_NB_CFG<17>
MAKE_BASE=TRUE
OMIT
34 21
34 21
SB_CLK100M_SATA_P
SB_CLK100M_SATA_N
PP6C4
PP6C5
1
SM PP
1
SM
PP
P4MM
14
OMIT
P4MM
OMIT
P4MM
NB_CFG<15>
I475
NB_CFG<14>
I476
NB_CFG<13>
I477
NB_CFG<12>
I478
NB_CFG<11>
I479
NB_CFG<10>
I481
NB_CFG<8>
I480
NB_CFG<6>
I482
NB_CFG<4>
I483
NB_CFG<3>
NC_NB_CFG<15>
MAKE_BASE=TRUE
NC_NB_CFG<14>
MAKE_BASE=TRUE
14
NC_NB_CFG<13>
MAKE_BASE=TRUE
14
NC_NB_CFG<12>
MAKE_BASE=TRUE
14
34 23
NC_NB_CFG<11>
MAKE_BASE=TRUE
D
34 23
SB_CLK14P3M_TIMER
SB_CLK48M_USBCTLR
PP6D9
PP6E0
1
SM PP
1
SM PP
OMIT
P4MM
OMIT
P4MM
14
NC_NB_CFG<10>
MAKE_BASE=TRUE
14
NC_NB_CFG<8>
MAKE_BASE=TRUE
PPVCORE_CPU
PP3V3_S5
PP2V5_S5
PP1V8_S3
PP1V2_S3
PP1V5_S0
PP1V05_S0
PP5V_S5
PP5V_S0
PP5V_S5
PP3V3_S5
PP3V3_S0
PP24V_S0
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
14
NC_NB_CFG<6>
MAKE_BASE=TRUE
14
NC_NB_CFG<4>
MAKE_BASE=TRUE
14
NC_NB_CFG<3>
MAKE_BASE=TRUE
I513
22
PCI_GNT3_L
TP_PCI_GNT3_L
MAKE_BASE=TRUE
SPARE USB PORT
34 22
PCI_CLK_SB
PCI_CLK_FW
PCI_CLK_SMC
PP6D0
PP626
PP627
1
SM PP
1
SM PP
1
SM PP
OMIT
OMIT
OMIT
P4MM
P4MM
P4MM
75 26 14 5
14
22
USB_F_N
USB_F_P
44 34
LAYOUT NOTE: PLACE NEAR NORTHBRIDGE
22
TP_USB_F_N
MAKE_BASE=TRUE
TP_USB_F_P
MAKE_BASE=TRUE
58 34
C
LAYOUT NOTE: PLACE NEAR SOUTHBRIDGE
38 21
38 21
38 21
VR_PWRGOOD_DELAY
NB_RST_IN_L_R
PP665
PP666
PP673
PP674
PP6E1
PP675
1
SM PP
1
SM PP
1
SM PP
1
SM PP
1
SM
PP
1
SM PP
OMIT
P4MM
OMIT
P4MM
19 13
INVERTER DOES NOT USE THIS SIGNAL
LVDS_BKLTEN
TP_LVDS_BKLTEN
19
MAKE_BASE=TRUE
NO_TEST=TRUE
IDE_PDIOR_L
IDE_PDIORDY
IDE_PDD<9>
PP6C6
PP6C7
PP6C8
1
SM PP
1
SM PP
1
SM PP
OMIT
P4MM
OMIT
P4MM
OMIT
P4MM
22 14
22 14
DMI_S2N_N<0>
DMI_S2N_P<0>
MEM_VREF_NB_0
MEM_VREF_NB_1
OMIT
P4MM
OMIT
P4MM
68
59
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
19 14
19 14
OMIT
P4MM
OMIT
P4MM
68
68
59
59
59
54 22
54 22
PCIE_B_D2R_P
PCIE_B_D2R_N
DMI_N2S_P<0>
DMI_N2S_N<0>
PP600
PP601
PP6D3
PP6D4
1
SM PP
1
SM PP
1
SM PP
1
SM PP
59
OMIT
P4MM
OMIT
P4MM
59
59
59
59
59
59
59
59
22 14
22 14
OMIT
P4MM
OMIT
P4MM
67 60 58 21 5
LPC_FRAME_L
SPI_SO
SPI_SI
PP6D8
PP612
PP613
1
SM PP
1
SM
PP
OMIT
OMIT
OMIT
P4MM
P4MM
P4MM
59
59
63 58 22
63 58 22
1
SM PP
B
ALL I2C BUSSES (PLACE IN ACCESSIBLE LOCATION TOP SIDE)
PP604
PP605
27
27
SMBUS_SB_SCL
SMBUS_SB_SDA
1
SM
1
SM
PP
PP
OMIT
P4MM
OMIT
P4MM
27
27
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
PP610
PP611
1
SM
PP
1
SM PP
OMIT
P4MM
OMIT
P4MM
A
P
7
e
r
59
84 13
84 13
NC_AUD_BI_PORT_G_L
NO_TEST=TRUE
NC_ALS_GAIN
NO_TEST=TRUE
NC_AUD_VREF_PORT_C
NO_TEST=TRUE
NC_AUD_VREF_PORT_D
NO_TEST=TRUE
NC_SMC_BATT_CHG_EN
NO_TEST=TRUE
NC_SMC_BATT_ISET
NO_TEST=TRUE
NC_SMC_BATT_TRICKLE_EN_L
NO_TEST=TRUE
NC_SMC_BATT_VSET
NO_TEST=TRUE
NC_SMC_P20
NO_TEST=TRUE
NC_SMC_P21
NO_TEST=TRUE
NC_SMC_P22
NO_TEST=TRUE
NC_SMC_P23
NO_TEST=TRUE
NC_SMC_P26
NO_TEST=TRUE
NC_SMC_P27
NO_TEST=TRUE
NC_SMC_SYS_ISET
NO_TEST=TRUE
NC_SMC_SYS_VSET
NO_TEST=TRUE
NC_SMS_X_AXIS
NO_TEST=TRUE
NC_SMS_Y_AXIS
NO_TEST=TRUE
NC_SMS_Z_AXIS
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PEG_R2D_C_N<0>
PEG_R2D_C_P<0>
PEG_R2D_C_N<1>
PEG_R2D_C_P<1>
PEG_R2D_C_N<2>
PEG_R2D_C_P<2>
PEG_R2D_C_N<3>
PEG_R2D_C_P<3>
PEG_R2D_C_N<4>
PEG_R2D_C_P<4>
PEG_R2D_C_N<5>
PEG_R2D_C_P<5>
PEG_R2D_C_N<6>
PEG_R2D_C_P<6>
PEG_R2D_C_N<7>
PEG_R2D_C_P<7>
PEG_R2D_C_N<8>
PEG_R2D_C_P<8>
PEG_R2D_C_N<9>
PEG_R2D_C_P<9>
84 13
84 13
84 13
84 13
84 13
84 13
84 13
84 13
m
i
l
73
73
IN
IN
IN
IN
NC_J7302_3
NC_J7302_6
NO_TEST=TRUE
NO_TEST=TRUE
68
68
NC_AUD_BI_PORT_E_L
NC_AUD_BI_PORT_E_R
NC_SMC_MEM_ISENSE
NC_AUD_BI_PORT_H_L
NC_AUD_BI_PORT_H_R
NC_AUD_VREF_PORT_B
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
59
68
68
68
IN
IN
IN
IN
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
a
n
i
29
29
y
r
60 6
60 59 21
60 34
67 60 58 23
67 60 58 23
60 58
60 59 58
60 58
60 23
76 58
94 85
94
75 8
75 8
75 8
75 8
75 8
75 8
75 8
75 23 14
75 21 7
75 26 14 5
26 23
84 77 58 26
77 58 23
80 79 77 58 23
XDP_BPM_L<3>
FUNC_TEST=TRUE
XDP_BPM_L<2>
FUNC_TEST=TRUE
XDP_BPM_L<1>
FUNC_TEST=TRUE
XDP_BPM_L<0>
FUNC_TEST=TRUE
XDP_DBRESET_L
FUNC_TEST=TRUE
SW_RST_BTN_L
FUNC_TEST=TRUE
POWER_BUTTON_L
FUNC_TEST=TRUE
LPC_AD<0>
FUNC_TEST=TRUE
LPC_AD<1>
FUNC_TEST=TRUE
LPC_AD<2>
FUNC_TEST=TRUE
LPC_AD<3>
FUNC_TEST=TRUE
LPC_FRAME_L
FUNC_TEST=TRUE
PM_CLKRUN_L
FUNC_TEST=TRUE
BOOT_LPC_SPI_L
FUNC_TEST=TRUE
DEBUG_RST_L
FUNC_TEST=TRUE
FWH_INIT_L
FUNC_TEST=TRUE
PCI_CLK_PORT80
FUNC_TEST=TRUE
INT_SERIRQ
FUNC_TEST=TRUE
PM_SUS_STAT_L
FUNC_TEST=TRUE
SMC_MD1
FUNC_TEST=TRUE
SMC_RST_L
FUNC_TEST=TRUE
SMC_NMI
FUNC_TEST=TRUE
SV_SET_UP
FUNC_TEST=TRUE
ISENSE_CAL_EN
FUNC_TEST=TRUE
INV_ENABLE_BL
FUNC_TEST=TRUE
LCD_PWM
FUNC_TEST=TRUE
CPU_VID<0>
FUNC_TEST=TRUE
CPU_VID<1>
FUNC_TEST=TRUE
CPU_VID<2>
FUNC_TEST=TRUE
CPU_VID<3>
FUNC_TEST=TRUE
CPU_VID<4>
FUNC_TEST=TRUE
CPU_VID<5>
FUNC_TEST=TRUE
CPU_VID<6>
FUNC_TEST=TRUE
PM_DPRSLPVR
FUNC_TEST=TRUE
CPU_DPRSTP_L
FUNC_TEST=TRUE
VR_PWRGOOD_DELAY
FUNC_TEST=TRUE
VR_PWRGD_CK410
FUNC_TEST=TRUE
ALL_SYS_PWRGD
FUNC_TEST=TRUE
PM_SLP_S4_L
FUNC_TEST=TRUE
PM_SLP_S3_L
FUNC_TEST=TRUE
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
SMC_TRST_L
SMC_TX_L
SMC_RX_L
SMC_MANUAL_RST_L
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
60 59 58
60 59 58
59
11 7
11 7
11 7
11 7
11 7
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
POWER_BUTTON_L
SW_RST_BTN_L
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
D
59 5
26 5
10
10
34 11
34 11
11
11 7
11 7
IN
IN
IN
IN
IN
IN
IN
NB_TSENS_HS_DXP
NB_TSENS_HS_DXN
CPU_XDP_CLK_N
CPU_XDP_CLK_P
ITPRESET_L
XDP_BPM_L<5>
XDP_BPM_L<4>
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
MISC GROUND VIAS
C
HOLE-VIA
1
ZH500
HOLE-VIA
1
ZH510
ZH511
1
HOLE-VIA
1
ZH520
ZH521
1
HOLE-VIA
1
ZH501
HOLE-VIA
HOLE-VIA
HOLE-VIA
1
ZH502
HOLE-VIA
1
ZH512
HOLE-VIA
1
ZH522
IN
IN
TP_MEM_B_A<15>
TP_MEM_B_A<14>
NO_TEST=TRUE
NO_TEST=TRUE
HOLE-VIA
1
ZH503
HOLE-VIA
1
ZH513
HOLE-VIA
1
ZH523
HOLE-VIA
1
84 13
84 13
ZH504
HOLE-VIA
1
ZH514
HOLE-VIA
1
ZH524
NO_TEST=TRUE
NO_TEST=TRUE
84
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
84
PEG_R2D_N<0>
PEG_R2D_P<0>
PEG_R2D_N<1>
PEG_R2D_P<1>
PEG_R2D_N<2>
PEG_R2D_P<2>
PEG_R2D_N<3>
PEG_R2D_P<3>
PEG_R2D_N<4>
PEG_R2D_P<4>
PEG_R2D_N<5>
PEG_R2D_P<5>
PEG_R2D_N<6>
PEG_R2D_P<6>
PEG_R2D_N<7>
PEG_R2D_P<7>
PEG_R2D_N<8>
PEG_R2D_P<8>
PEG_R2D_N<9>
PEG_R2D_P<9>
NO_TEST=TRUE
NO_TEST=TRUE
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PEG_D2R_N<0>
PEG_D2R_P<0>
PEG_D2R_N<1>
PEG_D2R_P<1>
PEG_D2R_N<2>
PEG_D2R_P<2>
PEG_D2R_N<3>
PEG_D2R_P<3>
PEG_D2R_N<4>
PEG_D2R_P<4>
PEG_D2R_N<5>
PEG_D2R_P<5>
PEG_D2R_N<6>
PEG_D2R_P<6>
PEG_D2R_N<7>
PEG_D2R_P<7>
PEG_D2R_N<8>
PEG_D2R_P<8>
PEG_D2R_N<9>
PEG_D2R_P<9>
PEG_D2R_N<10>
PEG_D2R_P<10>
PEG_D2R_N<11>
PEG_D2R_P<11>
PEG_D2R_N<12>
PEG_D2R_P<12>
PEG_D2R_N<13>
PEG_D2R_P<13>
PEG_D2R_N<14>
PEG_D2R_P<14>
PEG_D2R_N<15>
PEG_D2R_P<15>
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
84 13
84 13
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
84
84
HOLE-VIA
1
ZH505
HOLE-VIA
1
ZH515
HOLE-VIA
1
ZH525
B
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
84 13
84 13
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
84
84
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
84 13
84 13
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
84
84
HOLE-VIA
1
ZH506
HOLE-VIA
1
ZH516
HOLE-VIA
1
ZH526
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
84 13
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
84 13
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
84
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
84
NO_TEST=TRUE
NO_TEST=TRUE
HOLE-VIA
1
ZH507
HOLE-VIA
1
ZH517
HOLE-VIA
1
ZH527
84 13
84 13
NO_TEST=TRUE
NO_TEST=TRUE
84 13
84 13
HOLE-VIA
NO_TEST=TRUE
NO_TEST=TRUE
ZH508
1
HOLE-VIA
1
ZH518
HOLE-VIA
1
ZH528
84 13
84 13
NO_TEST=TRUE
NO_TEST=TRUE
84 13
84 13
HOLE-VIA
1
ZH509
HOLE-VIA
1
ZH519
HOLE-VIA
1
ZH529
NO_TEST=TRUE
NO_TEST=TRUE
84 13
84 13
84 13
84 13
PEG_R2D_C_N<10>
PEG_R2D_C_P<10>
PEG_R2D_C_N<11>
PEG_R2D_C_P<11>
PEG_R2D_C_N<12>
PEG_R2D_C_P<12>
PEG_R2D_C_N<13>
PEG_R2D_C_P<13>
PEG_R2D_C_N<14>
PEG_R2D_C_P<14>
PEG_R2D_C_N<15>
PEG_R2D_C_P<15>
PEG_R2D_N<10>
PEG_R2D_P<10>
PEG_R2D_N<11>
PEG_R2D_P<11>
PEG_R2D_N<12>
PEG_R2D_P<12>
PEG_R2D_N<13>
PEG_R2D_P<13>
PEG_R2D_N<14>
PEG_R2D_P<14>
PEG_R2D_N<15>
PEG_R2D_P<15>
NO_TEST=TRUE
NO_TEST=TRUE
FUNC TEST 1 OF 2
SYNC_MASTER=M51_HENRY
SYNC_DATE=08/04/2006
NO_TEST=TRUE
NO_TEST=TRUE
84 13
84 13
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
A
NO_TEST=TRUE
NO_TEST=TRUE
84 13
84 13
NO_TEST=TRUE
NO_TEST=TRUE
84 13
84 13
NO_TEST=TRUE
NO_TEST=TRUE
84 13
84 13
SIZE
DRAWING NUMBER
REV.
NO_TEST=TRUE
NO_TEST=TRUE
84 13
84 13
APPLE COMPUTER INC.
D
SCALE
NONE
051-7039
SHT
A
97
5
OF
8
6
5
4
3
2
1

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