Acer Extenza 5430_5530_5530G_Wistron_Olan_Rev-2M.pdf

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Olan (TM15") Block Diagram

DDR2

Project code: 91.4Z701.001

PCB P/N

: 48.4Z701.001

REVISION

: 07249-2M

PCB STACKUP

667/800MHz

SYSTEM DC/DC

TPS51125

INPUTS

DCBATOUT

667/800 MHz

8,9

AMD Giffin CPU

S1G2 (35W)

667/800MHz

638-Pin uFCPGA638

4,5,6,7

TOP

G792

45,46

VCC

OUTPUTS

5V_S5(7A)

3D3V_S5(7A)

DDR2

667/800 MHz

8,9

SYSTEM DC/DC

TPS51124

INPUTS

DCBATOUT

1D2V_S0(5A)

CRT

OUT

16X16

CRT

GND

BOTTOM

OUTPUTS

1D1V_S0(9A)

LCD

SILEGO SLG8SP628

CPU I/F

LVDS, CRT I/F

Port Replicator

CLK GEN.

North Bridge

AMD RS780M

INTEGRATED GRAHPICS

SYSTEM DC/DC

DVI

TPS51117

INPUTS

DCBATOUT

HDMI

OUTPUTS

1D8V_S3(10A)

PCIex16

VGA Borad

11,12,13

RT9026PFP

5V_S5

0D9V_S3

DDR_VREF_S3

Line In

Codec

ALC268

AZALIA

A-Link

4X4

LAN

Giga LAN

BCM5764M

RT9166

3D3V_S0

2D5V_S0

(300mA)

TXFM

RJ45

G957

3D3V_S0

1D5V_S0

(1A)

New card

South Bridge

AMD SB700

USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

ATA 66/100

ACPI 1.1

MIC In

PWR SW

TPS2231

PCIex1

G9161

3D3V_S5

1D2V_S5

(400mA)

Mini Card

Kedron a/b/g/n

CHARGER

BQ24745

INPUTS

OUTPUTS

CHG_PWR

DCBATOUT

18V

6.0A

100mA

Line Out

(No-SPDIF)

PCI

Cardbus

OZ711MZ

MS/MS Pro/xD

/MMC/SD/SD IO

5 in 1

OP AMP

G1454R

LPC I/F

PCI/PCI BRIDGE

20,21,22,23,24

PCMCIA

SLOT

UP+5V

LPC BUS

BIOS

Camera

INT.SPKR

CPU DC/DC

RJ11

MODEM

MDC Card

HDD SATA

ODD SATA

USB

SATA

Mini USB

Blue Tooth

Finger

Printer

KBC

Winbond

WPC775

Winbond

W25X80

LPC

DEBUG

CONN.

Launch

Buttom

USBX4

HP OUT

MIC IN

LINE IN

ISL6265HR

INPUTS OUTPUTS

VCC_CORE_S0_0

0~1.55V

DCBATOUT

0~1.55V

18A

VCC_CORE_S0_1

VDDNB

0~1.55V

USB

4 Port

Touch

Pad

INT.

UMA NODOCK

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

BLOCK DIAGRAM

Size

Document Number

Rev

Date: Monday, May 05, 2008

Olan

Sheet

-2M

5.Page 19: "HDMI1" add 2'nd source 62.10078.171.

6.Page 18: "F3" change to FUSE-1A6V-2-GP.

7.Page 30: "USBCN1" change to "20.F0765.020"

8.Page 26: ODD connector "SKT1" change to "62.10065.291"

9.Page 40: Add analog MIC schematic.

10.Page 46: Add "RN65" for NO duck LAN LED

11.Page All: Close PWR GAP

12.Page 03: Update "U18" foot print

13.Page 57: Add test point under Dimm Door

14.Page 55: "R32" pull hi from "3D3V_AUX_S5" to "BQ24745_VREF"

15.Page 41: Change audio AMP to G1454R41

16.Page 55: Change C34 size from 0402 to 0603

17.Page 57: Add EMI capacitor follow EMI recommend

18.Page 22: Add E-SATA schematic

===========================================================

2007/12/20

1.Page 12: "R109" change to "768R2F-1-GP"

2.Page 46: Remove "RN19" "RN21" "RN22" "RN23" "RN53" "RN54" "RN55" "RN56"

3.Page 46" connect U12 HDMI switch to PEG_TX

4.Page 51 Modify 5V & 3D3V 51125_ENTIP1 & 51125_ENTIP2 schematic.

5.Page 06: PH 300 ohmo on "CPU_DBREQ#"; PL 300 ohmo on "CPU_TEST21" & "CPU_TEST24"

6.Page 12: PH "SUS_STAT#" 10K ohmo to 3D3V_S0

7.Page 45: Add "DOCK1" PIN 51 "CRT_DEC#"

8.Page 46: Modify HDMI switch to "PS8122QFN48G-GP"

===========================================================

2007/12/25

1.Page 46: Connect "3D3V_S0" to U12 remove "3D3V_S0_PI"

2.Page 45: Add "R497" "R498" "R499" for DIS CRT switch

3.Page 46: Add Pi filter before dock & C818 C819 for VSYNC_5 and HSYNC_5

4.Page 37: Add "R618" PU for "AC/BAT_DET"

===========================================================

2007/12/26

1.Page 21: Swap USB port 8 and Port 10.

2.Page 45: Follow net swap report.

3.Page 41: Add "R633" DY PL "1451_SD"

4.Page 46: RN19~RN23, RN42~RN45 & RN65 change to SRN0J-10-GP

5.page 43: Add R634 ,U17 pin120 connect “SPI_WP_R#”

6.Page 30: Follow Homa modify "USBCN1"

===========================================================

2007/12/27

1.Page 11: NEW CARD PCIE channel change to channel 3.

2.Page 21: "DOCK_DT1#" change to "GEVENT7#" and DY 0 ohmo resistor

3.Page 37: Add "R618" PU for "AC/BAT_DET" on MXM pin 157, Connect MXM SMB with "RN53"

4.Page 45: Add Pi filter before dock

5.Page 18: change R113, R114, R106 and R99 to 33ohm. change C471, C468 and C466 to 2.2pf.

6.Page 43: Change R186 to 150ohm for PLT_RST1#_1 (KBC U20A)

7.Page 35: Change C86 to 150pf LAN_RST (LAN U8 )

8.Page 32: Change C631 to 150pf PLT_RST1#_MXM (U58 OZ711)

9.Page 37: Change C510 to 330pf for PLT_RST1#_MXM (MXM)

10.Page 33: Add C650 to 220pf for PCIRST1# (CR U67)

11.Page 38: Add C639 to 220pf for NEW_RST# (NEW U66)

12.Page 43: R181 change to 30KF for BOM integrate

13.Page 39: Change R226 to 470ohm for MINI_RST# (MINI MINIC1)

14.Page 12: Add 330pf C551 between R313 and ground for SYSREST# (NB U43C).

15.Page 40: Change C379 to 56pf for RESET# (AUDIO U24)

16.Page 06: Change R298 to 33ohm for LDT_RST#_CPU

17.Page 45: Change RN4 connect to "CRT_R_S" "CRT_G_S" "CRT_B_S"

18.Page 24: Change R89 to 10R2J-2-GP for BOM integrate

19.Page 46: Follow net swap report.

20.Page 57: Add Spring "GND1" "GND2"

===========================================================

2007/12/28

1.Page 57: Add EMI capacitor follow EMI recommend.

2.Page 45: ADD EC191 EC192 EC193 follow EMI recommend.

===========================================================

2007/12/28a

1.Page 40: Codec IC change to ALC268.

2.Page 41: ADD U69 G1412 AMP for Line out.

3.Page 33: Add EMI capacitor Follow EMI recommend

===========================================================

2007/12/31

1.Page 22: Change PlanarID to SB and ADD CLK_ID to identify Clock Gen.

2.Page 42: Modify "INTMIC1: to MONO MIC

3.Page 40: Modify ALC_268 to MONO MIC schematic, Add "DOCK_DT1#" on "GPIO1"

===========================================================

2008/01/02

1.Page 40: Change Speaker and Line-out channel.

2.Page 40: Chanhe "DOCK_DT1#" connect to GPIO3 U24 pin 3.

3.Page 40: Modify "MIC" and "Line_in" schematic.

4.Page 30: Modify "USBCN1" schematic follow Homa.

5.Page 43: Add "R654" 10K PU 3D3V_S0 for "FP_DETECT#".

6.Page 21: Add "R200" 10K PU 3D3V_S0 for "FP_ID"

7.Page 51: Add "R549" 0 ohm for "MXM_THER".

8.Page 40: Change R196 to 64.39225.6DL 39.2K.

9.Page 21: Remove "R397" "R489" R490" "R491", add "RN56" for component count.

===========================================================

2008/01/03

1.Page 50: Change C4 to SC1U10V3KX-3GP for BOM integrate

2.Page 55: Change C296 form SC1U25V5KX-1GP (P/N 78.10522.21L) to SC1U25V0KX-GP (P/N 78.10522.5BL)

3.Page 43: Remove "R188" "R177" "R185" "R189", add "RN56" for component count.

4.Page 46: Swap U12 Pin 29 & Pin 28; add C394, C395 D01u.

5.Page 22: Add U41 E-STAT solution

6.Page 21: Add R326 for NB_PWRGD

7.Page 48: Add R498 for NB_PWRGD

===========================================================

2008/01/03a

1.Page 46: Modify SM BUS PH resistor

2.Page 40: Add "R119" and "R177" for ALC268 GPIO1

===========================================================

2008/01/04

1.Page 22: Swap RN68 net

===========================================================

2008/01/04a

1.Page 57: Remove H23; H24.

2.Page 06: Remove R300, R301, change to "RN71"

===========================================================

2008/01/07

1.Page All: Follow Net swap report.

===========================================================

2008/01/07a

1.Page 22: Swap U41 Pin 3, 4 & Pin 17, 18.

===========================================================

2008/01/07b

1.Page 57: Add H23 screw holl.

===========================================================

2008/01/07c

1.Page All: Follow Net swap report.

===========================================================

2008/02/01

1.Page 45: Change "DOCK1" to 20.F1257.001.

===========================================================

2008/02/04

1.Page 40: Add R327, R328, EC200, EC201 for EMI solution.

===========================================================

2008/02/05

1.Page 22: Add R397 follow caystal FAE recommend.

2.Page All: Short 0 ohm resistor with PAD.

3.Page 18: Remove "D2" "D3" "D4" for ME & Layout

===========================================================

2008/02/13

1.Page 41 & 42: Modify Line-out jack connection.

===========================================================

2008/02/13a

1.Page 06: Follow AMD recommend Add & Dummy "R503" to PU "CPU_LDT_REQ#".

===========================================================

2008/02/13b

1.Page 06: Change "R503" to "R304" to PU "ALLOW_LDTSTOP".

2.Page 06 & 12: Remove net "CPU_LDT_REQ#" Replace with "ALLOW_LDTSTOP"

3.Page 21: Add "R134" & "R185" for "HDMI" on SB700 "GPIO0".

4.Page 42: Change "C400" "C401" to "R301" & "R218"

===========================================================

2008/03/03

page3, remove RN31 (control by SW)

page12,merge R105,R107 to RN29

merge R309,R310,R311 to RN72 (R309 can use 3K)

page14 merge R477,R476 to RN73

page16 RN1 change to 2 pcs 0ohm PAD "R476" "R477"

merge R29,R30 to RN53

page18 merge R106,R99 to RN75

merge R113,R114 to RN74

merge R283,R284 to RN30

merge R275,R276 to RN32

merge R319,R98 to RN31

page20 change R165,R164,R404,R403 to 0 ohm PAD (only use for strap,don't need 22 ohm)

page21 merge R170,R159 to RN34

merge R162,R160 to RN33

R185 for Dock(input can't floating)

page22 Short R140,R138

C672,C671,C673,C674 for E-SATA only,need add DIS

check with SW to remove CLK_ID setting(use SMBus)

dummy all E-SATA re-driver

change RN67,RN68 to PAD

page24 merge R437,R421 to RN35

merge R344,R355 to RN36

del R360,R366,merge R361,R365 to RN37

page35 change R265,R263,R67,R87,R72,R269,R270,R79,R260,R58,R54,R56,R38,R44,R42,R46,R74,R83 TO 0ohm PAD

page37 change r456 to PAD

page39 check R224/R225,R222/R229, need confirm spec

page40 check R327,R328 with EMI

change RN55,R325 to PAD

Modify schematic for current leackage on "DOCK_DT1#"

R119 for Dock (input can't floating)

page42 merge R217,R220 to RN55

merge R214,R215 to RN67

merge R475,R479 to RN76 (need change to 48 ohm)

page44 change ER1, ER2,ER4 to PAD

dummy EC69

change ER3 to 33 ohm

page47 change R316 to PAD

page48 level shift for NB_PWRGD

page50 change R12,R13,R14,R3,R4,R7 to PAD

page53 change R261 to PAD

page54 change R317,R318 to PAD

page55 change R148,R147,R132,R131 to PAD

merge R28,R32,R31,R37 to RN77 (please take care R32 power)

===========================================================

2008/03/04

1.Page 26: Modify "SKT1" ODD connector.

2.Page 45: Merge "R292" "R293" to "RN68".

3.Page 51: change R416,R441 to PAD for noise issue.

4.Page 16: "F2" change to "69.50007.A31".

===========================================================

2008/03/04b

1.Page 51: change R416,R442 to PAD and DY "R441" for noise issue.

2.Page 17: "LED3" change to "3D3V_S5" "LED2" change to "3D3V_AUX_S5".

3.Page 30: Modify "USBCN1" pin define.

4.Page 40: Remove "C377" "C379" short them

5.Page 40: Remove "R177" for new INTMIC connector

6.Page 42: Modify "INTMIC" schematic.

7.Page 45: Merge R497, R498, R499 to RN68; R287, R286, R289 to RN78.

8.Page 16: Add RN79 for ESD.

9.Page 45: "DOCK1" "PIN S51" change to "CRT_IN#_R" for ESD.

10.Page 45: Add "RN80" for ESD

11.Page 56: Add "D30" on "BAT_IN#" for ESD, Change "RN59" to 8P4R for "BAT_IN#" ESD

===========================================================

2008/03/05

1.Page 32: Add "R220" and Dummy for "PME" issue.

2.Page 39: Change "3D3V_S5_MINI1" to "3D3V_S5" and Change "3D3V_S0_MINI" to "3D3V_S5".

3.Page 17: Merge "R485" "R486" to "RN81"; Merge "R487" "R488" to "RN82".

4.Page 17: Change "R473" to "453R2F-1-GP"; Change "R480" to "150R2F-1-GP".

5.Page 14: Merge "R179" "R180" to "RN83".

6.Page All: Follow Swap report.

===========================================================

2008/03/06

1.Page 30: "USBCN1" pin 15 change to GND.

2.Page 22: Remove "U41" relative schematic.

3.Page 40: "RN41" change to 4P2R

4.Page 42: Merge "R474" "R475" to "RN84".

5.Page 42: Change "EC6" "EC7" "EC8" "EC9" to 0603

6.Page 40: Change "EC200" "EC201" to 0603

7.Page 38: "U66" change to 74.00577.A73

8.Page 57: ADD EMI capacitor "EC203" ~ "EC220".

9.Page 40: Merge "R329" "R330" "R325" to "RN85" for ESD.

10.Page 42: Short "RN67" with PAD.

===========================================================

2008/03/06a

1.Page 51: Change "TC17" "TC10" to 77.21561.00L & mount.

2.Page 50: Change "C7" "C8" to 77.21561.00L & mount.

3.Page 52: Change "TC19" to 79.10712.L02.

4.Page 55: Add "C826" for Vendor suggest added decoupling capacitor in CSSN to ground.

===========================================================

2008/03/07

1.Page 55: Change "D9" to 83.R0203.08F & mount.

2.Page 57: Add Spring "GND5 and EMI capacitor "EC221" ~ "EC229".

===========================================================

2008/03/10

1.Page 57: Add "GND11" for EMI, "GND8" "GND9" "GND10" change to "34.15F09.001".

2.Page 52: Change "TC21" to SE100U25VM-L1-GP.

3.Page All: Follow Swap net.

===========================================================

2008/03/10a

1.Page 55: Change "TC21" to SE100U25VM-L1-GP.

2.Page 57: Remove "GND6" "GND7".

===========================================================

2008/03/11

UMA NODOCK

1.Page 57: Remove "EC204" "EC205".

===========================================================

2008/03/11a

1.Page 40: "R194" change to "51R2J-2-GP".

2.Page 29: "R235" change to "15R2J-GP" & DY "C424".

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

3.Page 21: Change "RN33" to "R655" & "R656" with "27R2J-1-GP"; Change "RN34" to "SRN47J-7-GP"; UNdummy "EC61" "EC63".

Hsien 221, Taiwan, R.O.C.

Taipei

4.Page 48: Add "U70" for "NB_PWRGD" level shift.

===========================================================

Title

Wistron Corporation

HISTORY

Size

Document Number

Rev

Date: Friday, April 18, 2008

Olan

Sheet

-1

SC_0205

2R3J-GP

C348

Do Not Stuff

C337

SC10U10V5ZY-1GP

C315

SC10U10V5ZY-1GP

C320

SCD1U10V2KX-4GP

C318

SCD1U10V2KX-4GP

C321

SCD1U10V2KX-4GP

C329

SCD1U10V2KX-4GP

C343

SCD1U10V2KX-4GP

C347

SCD1U10V2KX-4GP

3D3V_S0

Do Not Stuff

R173

3D3V_CLK_VDD

3D3V_S0

R174

C333

SCD1U10V2KX-4GP

3D3V_48MPWR_S0

C342

SC1U10V2KX-1GP

3000mA.80ohm

Due to PLL issue on current clock chip, the SBlink clock

need to come from SRC clocks for RS740 and RS780.

Future clock chip revision will fix this.

-1_0301

3D3V_S0

Do Not Stuff

R139

1D1V_S0

R145

Clock chip has internal serial terminations

for differencial pairs, external resistors are

reserved for debug purpose.

1D1V_CLK_VDDIO

Do Not Stuff

U18

1D1V_CLK_VDDIO

GEN_XTAL_IN

GEN_XTAL_OUT

CLK_SMBCLK

CLK_SMBDAT

G86

G87

Do Not Stuff

2ND = 82.30005.951

C317

SC10U10V5ZY-1GP

C314

SC10U10V5ZY-1GP

C344

SCD1U10V2KX-4GP

C322

SCD1U10V2KX-4GP

C341

SCD1U10V2KX-4GP

C336

SCD1U10V2KX-4GP

Do Not Stuff

R171

C319

SCD1U10V2KX-4GP

3D3V_CLK_VDD

C340

SC33P50V2JN

X-14D31818M-35GP

82.30005.891

C346

VDDATIG

VDDATIG_IO

VDDCPU

VDDCPU_IO

VDDSRC

VDDSRC_IO

VDDSB_SRC

VDDSB_SRC_IO

VDDSATA

VDD

VDDHTT

VDDREF

VDD48

PD#

SMBCLK

SMBDAT

ATIG0T_LPRS

ATIG0C_LPRS

ATIG1T_LPRS

ATIG1C_LPRS

CLKREQ0#

CLKREQ1#

CLKREQ2#

CLKREQ3#

CLKREQ4#

CPUKG0T_LPRS

CPUKG0C_LPRS

SB_0108

CL=20pF±0.2pF

SC33P50V2JN

1109

SMBC0_SB 8,9,21

SMBD0_SB 8,9,21

CLK_PCIE_PEG 37

CLK_PCIE_PEG# 37

CLK_NB_GFX 12

CLK_NB_GFX# 12

3D3V_CLK_VDD

Do Not Stuff

R167

C330

SC1U10V2KX-1GP

SC_0205

VDD_REF

3D3V_48MPWR_S0

PD#

-1_0301

CLKREQ0#

CLKREQ1#

CLKREQ2#

CLKREQ3#

CLKREQ4#

TP64

TP144

TP146

TP147

TP154

Do Not Stuff

R141

CLKREQ# Internal

pull high

CPU_CLK

CPU_CLK#

CLK48_USB 21

Do Not Stuff

33R2J-2-GP

20 CLK_PCIE_SB

20 CLK_PCIE_SB#

35 CLK_PCIE_LAN

35 CLK_PCIE_LAN#

12 CLK_NB_GPPSB

12 CLK_NB_GPPSB#

39 CLK_PCIE_MINI1

39 CLK_PCIE_MINI1#

38 CLK_PCIE_NEW

38 CLK_PCIE_NEW#

Do Not Stuff

TP66

Do Not Stuff

TP65

CLK_SRC0T_LPRS

CLK_SRC0C_LPRS

SC_0205

SRC0T_LPRS

SRC0C_LPRS

48MHZ_0

SRC1T_LPRS

SRC1C_LPRS

SRC2T_LPRS

REF0/SEL_HTT66

SRC2C_LPRS

REF1/SEL_SATA

SRC3T_LPRS

REF2/SEL_27

SRC3C_LPRS

SRC4T_LPRS

SRC4C_LPRS

SRC6T/SATAT_LPRS

GNDSATA

SRC6C/SATAC_LPRS

GNDATIG

SRC7T_LPRS/27MHZ_SS

GND

SRC7C_LPRS/27MHZ_NS

GNDHTT

GNDREF

GNDCPU

SB_SRC0T_LPRS

GND48

SB_SRC0C_LPRS

SB_SRC1T_LPRS

GNDSRC

SB_SRC1C_LPRS

GNDSRC

GNDSB_SRC

HTT0T_LPRS/66M

HTT0C_LPRS/66M

ICS9LPRS480BKLFT-GP

CLK_48

REF0

REF1

REF2

R172

EC65

Do Not Stuff

NB CLOCK INPUT TABLE

NB CLOCKS

HT_REFCLKP

66M SE(SINGLE END)

12 CLK_NBHT_CLK

12 CLK_NBHT_CLK#

RS740

RX780

100M DIFF

14M SE (1.8V)

100M DIFF

RS780

100M DIFF

14M SE (1.1V)

vref

100M DIFF(IN/OUT)*

NC or 100M DIFF OUTPUT

GND

HT_REFCLKN

REFCLK_P

REFCLK_N

GFX_REFCLK

GPP_REFCLK

GPPSB_REFCLK

14M SE (3.3V)

100M DIFF

71.09480.A03

2nd = SLG:71.08628.003

-1_0310 change to 71.09480.A03

3D3V_S0

R146

PD#

10KR2J-3-GP

100M DIFF

3D3V_S0

* RS780 can be used as clock buffer to output two PCIE referecence clocks

By deault, chip will configured as input mode, BIOS can program it to output mode.

R151

Do Not Stuff

R156

Do Not Stuff

R154

10KR2J-3-GP

SEL_SATA

REF1

REF0

REF1

REF2

SEL_HTT66

REF0

* default

100 MHz non-spreading differential SRC clock

100 MHz spreading differential SRC clock

66 MHz 3.3V single ended HTT clock

100 MHz differential HTT clock

REF0

150R2F-1-GP

75R2F-2-GP

R150

CLK_NB_14M 12

UMA NODOCK

R149

Wistron Corporation

OSC_14M_NB

RS780M 1.1V 158R/90.9R

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

R152

Do Not Stuff

R157

Do Not Stuff

R155

Do Not Stuff

CPU_CLK(200MHz)

CLKGEN_ICS9LPRS480

Size

Document Number

Rev

Olan

Sheet

-2M

Date: Monday, May 05, 2008

1D2V_S0

Place close to socket

SC4D7U6D3V5KX-3GP

SCD22U6D3V2KX-1GP

SC180P50V2JN-1GP

1.5Amp

C456

U38A

C450

C453

C481

C478

C454

C476

VLDT_A0

VLDT_A1

VLDT_A2

VLDT_A3

HT LINK

VLDT_B0

VLDT_B1

VLDT_B2

VLDT_B3

AE2

AE3

AE4

AE5

AD1

AC1

AC2

AC3

AB1

AA1

AA2

AA3

AD4

AD3

AD5

AC5

AB4

AB3

AB5

AA5

HT_CPU_NB_CAD_H0

HT_CPU_NB_CAD_L0

HT_CPU_NB_CAD_H1

HT_CPU_NB_CAD_L1

HT_CPU_NB_CAD_H2

HT_CPU_NB_CAD_L2

HT_CPU_NB_CAD_H3

HT_CPU_NB_CAD_L3

HT_CPU_NB_CAD_H4

HT_CPU_NB_CAD_L4

HT_CPU_NB_CAD_H5

HT_CPU_NB_CAD_L5

HT_CPU_NB_CAD_H6

HT_CPU_NB_CAD_L6

HT_CPU_NB_CAD_H7

HT_CPU_NB_CAD_L7

HT_CPU_NB_CAD_H8

HT_CPU_NB_CAD_L8

HT_CPU_NB_CAD_H9

HT_CPU_NB_CAD_L9

HT_CPU_NB_CAD_H10

HT_CPU_NB_CAD_L10

HT_CPU_NB_CAD_H11

HT_CPU_NB_CAD_L11

HT_CPU_NB_CAD_H12

HT_CPU_NB_CAD_L12

HT_CPU_NB_CAD_H13

HT_CPU_NB_CAD_L13

HT_CPU_NB_CAD_H14

HT_CPU_NB_CAD_L14

HT_CPU_NB_CAD_H15

HT_CPU_NB_CAD_L15

HT_NB_CPU_CAD_H0

HT_NB_CPU_CAD_L0

HT_NB_CPU_CAD_H1

HT_NB_CPU_CAD_L1

HT_NB_CPU_CAD_H2

HT_NB_CPU_CAD_L2

HT_NB_CPU_CAD_H3

HT_NB_CPU_CAD_L3

HT_NB_CPU_CAD_H4

HT_NB_CPU_CAD_L4

HT_NB_CPU_CAD_H5

HT_NB_CPU_CAD_L5

HT_NB_CPU_CAD_H6

HT_NB_CPU_CAD_L6

HT_NB_CPU_CAD_H7

HT_NB_CPU_CAD_L7

HT_NB_CPU_CAD_H8

HT_NB_CPU_CAD_L8

HT_NB_CPU_CAD_H9

HT_NB_CPU_CAD_L9

HT_NB_CPU_CAD_H10

HT_NB_CPU_CAD_L10

HT_NB_CPU_CAD_H11

HT_NB_CPU_CAD_L11

HT_NB_CPU_CAD_H12

HT_NB_CPU_CAD_L12

HT_NB_CPU_CAD_H13

HT_NB_CPU_CAD_L13

HT_NB_CPU_CAD_H14

HT_NB_CPU_CAD_L14

HT_NB_CPU_CAD_H15

HT_NB_CPU_CAD_L15

HT_NB_CPU_CLK_H0

HT_NB_CPU_CLK_L0

HT_NB_CPU_CLK_H1

HT_NB_CPU_CLK_L1

HT_NB_CPU_CTL_H0

HT_NB_CPU_CTL_L0

HT_NB_CPU_CTL_H1

HT_NB_CPU_CTL_L1

L0_CADIN_H0

L0_CADIN_L0

L0_CADIN_H1

L0_CADIN_L1

L0_CADIN_H2

L0_CADIN_L2

L0_CADIN_H3

L0_CADIN_L3

L0_CADIN_H4

L0_CADIN_L4

L0_CADIN_H5

L0_CADIN_L5

L0_CADIN_H6

L0_CADIN_L6

L0_CADIN_H7

L0_CADIN_L7

L0_CADIN_H8

L0_CADIN_L8

L0_CADIN_H9

L0_CADIN_L9

L0_CADIN_H10

L0_CADIN_L10

L0_CADIN_H11

L0_CADIN_L11

L0_CADIN_H12

L0_CADIN_L12

L0_CADIN_H13

L0_CADIN_L13

L0_CADIN_H14

L0_CADIN_L14

L0_CADIN_H15

L0_CADIN_L15

L0_CLKIN_H0

L0_CLKIN_L0

L0_CLKIN_H1

L0_CLKIN_L1

L0_CTLIN_H0

L0_CTLIN_L0

L0_CTLIN_H1

L0_CTLIN_L1

SKT-CPU638P-GP-U1

L0_CADOUT_H0

L0_CADOUT_L0

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H15

L0_CADOUT_L15

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

HT_CPU_NB_CLK_H0 11

HT_CPU_NB_CLK_L0 11

HT_CPU_NB_CLK_H1 11

HT_CPU_NB_CLK_L1 11

HT_CPU_NB_CTL_H0 11

HT_CPU_NB_CTL_L0 11

HT_CPU_NB_CTL_H1 11

HT_CPU_NB_CTL_L1 11

2ND = 62.10040.471

62.10055.111

SKT-BGA638H176

UMA NODOCK

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_HT_LINK I/F_(1/4)

Size

Document Number

Rev

Date: Friday, April 18, 2008

Olan

Sheet

-1

U38C

MEM:DATA

MEM_MA_DATA0

MEM_MA_DATA1

MEM_MA_DATA2

MEM_MA_DATA3

MEM_MA_DATA4

MEM_MA_DATA5

MEM_MA_DATA6

MEM_MA_DATA7

MEM_MA_DATA8

MEM_MA_DATA9

MEM_MA_DATA10

MEM_MA_DATA11

MEM_MA_DATA12

MEM_MA_DATA13

MEM_MA_DATA14

MEM_MA_DATA15

MEM_MA_DATA16

MEM_MA_DATA17

MEM_MA_DATA18

MEM_MA_DATA19

MEM_MA_DATA20

MEM_MA_DATA21

MEM_MA_DATA22

MEM_MA_DATA23

MEM_MA_DATA24

MEM_MA_DATA25

MEM_MA_DATA26

MEM_MA_DATA27

MEM_MA_DATA28

MEM_MA_DATA29

MEM_MA_DATA30

MEM_MA_DATA31

MEM_MA_DATA32

MEM_MA_DATA33

MEM_MA_DATA34

MEM_MA_DATA35

MEM_MA_DATA36

MEM_MA_DATA37

MEM_MA_DATA38

MEM_MA_DATA39

MEM_MA_DATA40

MEM_MA_DATA41

MEM_MA_DATA42

MEM_MA_DATA43

MEM_MA_DATA44

MEM_MA_DATA45

MEM_MA_DATA46

MEM_MA_DATA47

MEM_MA_DATA48

MEM_MA_DATA49

MEM_MA_DATA50

MEM_MA_DATA51

MEM_MA_DATA52

MEM_MA_DATA53

MEM_MA_DATA54

MEM_MA_DATA55

MEM_MA_DATA56

MEM_MA_DATA57

MEM_MA_DATA58

MEM_MA_DATA59

MEM_MA_DATA60

MEM_MA_DATA61

MEM_MA_DATA62

MEM_MA_DATA63

MEM_MA_DM0

MEM_MA_DM1

MEM_MA_DM2

MEM_MA_DM3

MEM_MA_DM4

MEM_MA_DM5

MEM_MA_DM6

MEM_MA_DM7

MEM_MA_DQS0_P

MEM_MA_DQS0_N

MEM_MA_DQS1_P

MEM_MA_DQS1_N

MEM_MA_DQS2_P

MEM_MA_DQS2_N

MEM_MA_DQS3_P

MEM_MA_DQS3_N

MEM_MA_DQS4_P

MEM_MA_DQS4_N

MEM_MA_DQS5_P

MEM_MA_DQS5_N

MEM_MA_DQS6_P

MEM_MA_DQS6_N

MEM_MA_DQS7_P

MEM_MA_DQS7_N

Place near to CPU

4.7u x 4

C185

SC4D7U6D3V5KX-3GP

C183

SC4D7U6D3V5KX-3GP

C184

SC4D7U6D3V5KX-3GP

C186

SC4D7U6D3V5KX-3GP

0.22u X 2

SCD22U6D3V2KX-1GP

C49

C164

C181

SC180P50V2JN-1GP

C180

SC180P50V2JN-1GP

C54

180P x 6

C52

SC180P50V2JN-1GP

C48

SC180P50V2JN-1GP

C72

SC180P50V2JN-1GP

0D9V_S3

CLOSE TO CPU

U38B

1D8V_S3

MEM:CMD/CTRL/CLK

VTT5

VTT6

VTT7

VTT8

VTT9

MEMZP

MEMZN

AF10

AE10

H16

T19

V22

U21

V19

T20

U19

U20

V20

J22

J20

N19

N20

E16

F16

Y16

AA16

P19

P20

N21

M20

N22

M19

M22

L20

M24

L21

L19

K22

R21

L22

K20

V24

K24

K19

R20

R23

J21

R19

T22

T24

MEMZP

MEMZN

RSVD_M1

MA0_ODT0

MA0_ODT1

MA1_ODT0

MA1_ODT1

MA0_CS_L0

MA0_CS_L1

MA1_CS_L0

MA1_CS_L1

MA_CKE0

MA_CKE1

MA_CLK_H5

MA_CLK_L5

MA_CLK_H1

MA_CLK_L1

MA_CLK_H7

MA_CLK_L7

MA_CLK_H4

MA_CLK_L4

MA_ADD0

MA_ADD1

MA_ADD2

MA_ADD3

MA_ADD4

MA_ADD5

MA_ADD6

MA_ADD7

MA_ADD8

MA_ADD9

MA_ADD10

MA_ADD11

MA_ADD12

MA_ADD13

MA_ADD14

MA_ADD15

MA_BANK0

MA_BANK1

MA_BANK2

MA_RAS_L

MA_CAS_L

MA_WE_L

SKT-CPU638P-GP-U1

VTT_SENSE

MEMVREF

RSVD_M2

MB0_ODT0

MB0_ODT1

MB1_ODT0

MB0_CS_L0

MB0_CS_L1

MB1_CS_L0

MB_CKE0

MB_CKE1

MB_CLK_H5

MB_CLK_L5

MB_CLK_H1

MB_CLK_L1

MB_CLK_H7

MB_CLK_L7

MB_CLK_H4

MB_CLK_L4

MB_ADD0

MB_ADD1

MB_ADD2

MB_ADD3

MB_ADD4

MB_ADD5

MB_ADD6

MB_ADD7

MB_ADD8

MB_ADD9

MB_ADD10

MB_ADD11

MB_ADD12

MB_ADD13

MB_ADD14

MB_ADD15

MB_BANK0

MB_BANK1

MB_BANK2

MB_RAS_L

MB_CAS_L

MB_WE_L

Y10

VTT_SENSE

W17

B18

W26

W23

Y26

V26

W25

U22

J25

H26

P22

R22

A17

A18

AF18

AF17

R26

R25

P24

N24

P26

N23

N26

L23

N25

L24

M26

K26

T26

L26

L25

W24

J23

J24

R24

U26

J26

U25

U24

U23

TP5

Do Not Stuff

VREF_DDR_CLAW

1D8V_S3

R257

39D2R2F-L-GP

R258

39D2R2F-L-GP

TP7

D10

C10

B10

AD10

VTT1

VTT2

VTT3

VTT4

W10

AC10

AB10

AA10

A10

C81

SCD1U10V2KX-4GP

RN3

MEM_RSVD_M1

C77

8,10 MEM_MA0_ODT0

8,10 MEM_MA0_ODT1

MEM_MB0_ODT0 9,10

MEM_MB0_ODT1 9,10

MEM_MB0_CS#0 9,10

MEM_MB0_CS#1 9,10

MEM_MB_CKE0 9,10

MEM_MB_CKE1 9,10

MEM_RSVD_M2

TP84

SRN1KJ-7-GP

C59

8,10 MEM_MA0_CS#0

8,10 MEM_MA0_CS#1

8,10 MEM_MA_CKE0

8,10 MEM_MA_CKE1

MEM_MA_CLK0_P

MEM_MA_CLK0_N

MEM_MA_CLK1_P

MEM_MA_CLK1_N

MEM_MB_CLK0_P

MEM_MB_CLK0_N

MEM_MB_CLK1_P

MEM_MB_CLK1_N

G12

F12

H14

G14

H11

H12

C13

E13

H15

E15

E17

H17

E14

F14

C17

G17

G18

C19

D22

E20

E18

F18

B22

C23

F20

F22

H24

J19

E21

E22

H20

H22

Y24

AB24

AB22

AA21

W22

W21

Y22

AA22

Y20

AA20

AA18

AB18

AB21

AD21

AD19

Y18

AD17

W16

W14

Y14

Y17

AB17

AB15

AD15

AB13

AD13

Y12

W11

AB14

AA14

AB12

AA12

E12

C15

E19

F24

AC24

Y19

AB16

Y13

G13

H13

G16

G15

C22

C21

G22

G21

AD23

AC23

AB19

AB20

Y15

W15

W12

W13

MA_DATA0

MA_DATA1

MA_DATA2

MA_DATA3

MA_DATA4

MA_DATA5

MA_DATA6

MA_DATA7

MA_DATA8

MA_DATA9

MA_DATA10

MA_DATA11

MA_DATA12

MA_DATA13

MA_DATA14

MA_DATA15

MA_DATA16

MA_DATA17

MA_DATA18

MA_DATA19

MA_DATA20

MA_DATA21

MA_DATA22

MA_DATA23

MA_DATA24

MA_DATA25

MA_DATA26

MA_DATA27

MA_DATA28

MA_DATA29

MA_DATA30

MA_DATA31

MA_DATA32

MA_DATA33

MA_DATA34

MA_DATA35

MA_DATA36

MA_DATA37

MA_DATA38

MA_DATA39

MA_DATA40

MA_DATA41

MA_DATA42

MA_DATA43

MA_DATA44

MA_DATA45

MA_DATA46

MA_DATA47

MA_DATA48

MA_DATA49

MA_DATA50

MA_DATA51

MA_DATA52

MA_DATA53

MA_DATA54

MA_DATA55

MA_DATA56

MA_DATA57

MA_DATA58

MA_DATA59

MA_DATA60

MA_DATA61

MA_DATA62

MA_DATA63

MA_DM0

MA_DM1

MA_DM2

MA_DM3

MA_DM4

MA_DM5

MA_DM6

MA_DM7

MA_DQS_H0

MA_DQS_L0

MA_DQS_H1

MA_DQS_L1

MA_DQS_H2

MA_DQS_L2

MA_DQS_H3

MA_DQS_L3

MA_DQS_H4

MA_DQS_L4

MA_DQS_H5

MA_DQS_L5

MA_DQS_H6

MA_DQS_L6

MA_DQS_H7

MA_DQS_L7

SKT-CPU638P-GP-U1

MB_DATA0

MB_DATA1

MB_DATA2

MB_DATA3

MB_DATA4

MB_DATA5

MB_DATA6

MB_DATA7

MB_DATA8

MB_DATA9

MB_DATA10

MB_DATA11

MB_DATA12

MB_DATA13

MB_DATA14

MB_DATA15

MB_DATA16

MB_DATA17

MB_DATA18

MB_DATA19

MB_DATA20

MB_DATA21

MB_DATA22

MB_DATA23

MB_DATA24

MB_DATA25

MB_DATA26

MB_DATA27

MB_DATA28

MB_DATA29

MB_DATA30

MB_DATA31

MB_DATA32

MB_DATA33

MB_DATA34

MB_DATA35

MB_DATA36

MB_DATA37

MB_DATA38

MB_DATA39

MB_DATA40

MB_DATA41

MB_DATA42

MB_DATA43

MB_DATA44

MB_DATA45

MB_DATA46

MB_DATA47

MB_DATA48

MB_DATA49

MB_DATA50

MB_DATA51

MB_DATA52

MB_DATA53

MB_DATA54

MB_DATA55

MB_DATA56

MB_DATA57

MB_DATA58

MB_DATA59

MB_DATA60

MB_DATA61

MB_DATA62

MB_DATA63

MB_DM0

MB_DM1

MB_DM2

MB_DM3

MB_DM4

MB_DM5

MB_DM6

MB_DM7

MB_DQS_H0

MB_DQS_L0

MB_DQS_H1

MB_DQS_L1

MB_DQS_H2

MB_DQS_L2

MB_DQS_H3

MB_DQS_L3

MB_DQS_H4

MB_DQS_L4

MB_DQS_H5

MB_DQS_L5

MB_DQS_H6

MB_DQS_L6

MB_DQS_H7

MB_DQS_L7

C11

A11

A14

B14

G11

E11

D12

A13

A15

A16

A19

A20

C14

D14

C18

D18

D20

A21

D24

C25

B20

C20

B24

C24

E23

E24

G25

G26

C26

D26

G23

G24

AA24

AA23

AD24

AE24

AA26

AA25

AD26

AE25

AC22

AD22

AE20

AF20

AF24

AF23

AC20

AD20

AD18

AE18

AC14

AD14

AF19

AC18

AF16

AF15

AF13

AC12

AB11

Y11

AE14

AF14

AF11

AD11

A12

B16

A22

E25

AB26

AE22

AC16

AD12

C12

B12

D16

C16

A24

A23

F26

E26

AC25

AC26

AF21

AF22

AE16

AD16

AF12

AE12

MEM_MB_DATA0 9

MEM_MB_DATA1 9

MEM_MB_DATA2 9

MEM_MB_DATA3 9

MEM_MB_DATA4 9

MEM_MB_DATA5 9

MEM_MB_DATA6 9

MEM_MB_DATA7 9

MEM_MB_DATA8 9

MEM_MB_DATA9 9

MEM_MB_DATA10 9

MEM_MB_DATA11 9

MEM_MB_DATA12 9

MEM_MB_DATA13 9

MEM_MB_DATA14 9

MEM_MB_DATA15 9

MEM_MB_DATA16 9

MEM_MB_DATA17 9

MEM_MB_DATA18 9

MEM_MB_DATA19 9

MEM_MB_DATA20 9

MEM_MB_DATA21 9

MEM_MB_DATA22 9

MEM_MB_DATA23 9

MEM_MB_DATA24 9

MEM_MB_DATA25 9

MEM_MB_DATA26 9

MEM_MB_DATA27 9

MEM_MB_DATA28 9

MEM_MB_DATA29 9

MEM_MB_DATA30 9

MEM_MB_DATA31 9

MEM_MB_DATA32 9

MEM_MB_DATA33 9

MEM_MB_DATA34 9

MEM_MB_DATA35 9

MEM_MB_DATA36 9

MEM_MB_DATA37 9

MEM_MB_DATA38 9

MEM_MB_DATA39 9

MEM_MB_DATA40 9

MEM_MB_DATA41 9

MEM_MB_DATA42 9

MEM_MB_DATA43 9

MEM_MB_DATA44 9

MEM_MB_DATA45 9

MEM_MB_DATA46 9

MEM_MB_DATA47 9

MEM_MB_DATA48 9

MEM_MB_DATA49 9

MEM_MB_DATA50 9

MEM_MB_DATA51 9

MEM_MB_DATA52 9

MEM_MB_DATA53 9

MEM_MB_DATA54 9

MEM_MB_DATA55 9

MEM_MB_DATA56 9

MEM_MB_DATA57 9

MEM_MB_DATA58 9

MEM_MB_DATA59 9

MEM_MB_DATA60 9

MEM_MB_DATA61 9

MEM_MB_DATA62 9

MEM_MB_DATA63 9

MEM_MB_DM0

MEM_MB_DM1

MEM_MB_DM2

MEM_MB_DM3

MEM_MB_DM4

MEM_MB_DM5

MEM_MB_DM6

MEM_MB_DM7

8,10

MEM_MA_ADD0

MEM_MA_ADD1

MEM_MA_ADD2

MEM_MA_ADD3

MEM_MA_ADD4

MEM_MA_ADD5

MEM_MA_ADD6

MEM_MA_ADD7

MEM_MA_ADD8

MEM_MA_ADD9

MEM_MA_ADD10

MEM_MA_ADD11

MEM_MA_ADD12

MEM_MA_ADD13

MEM_MA_ADD14

MEM_MA_ADD15

MEM_MB_ADD0 9,10

MEM_MB_ADD1 9,10

MEM_MB_ADD2 9,10

MEM_MB_ADD3 9,10

MEM_MB_ADD4 9,10

MEM_MB_ADD5 9,10

MEM_MB_ADD6 9,10

MEM_MB_ADD7 9,10

MEM_MB_ADD8 9,10

MEM_MB_ADD9 9,10

MEM_MB_ADD10 9,10

MEM_MB_ADD11 9,10

MEM_MB_ADD12 9,10

MEM_MB_ADD13 9,10

MEM_MB_ADD14 9,10

MEM_MB_ADD15 9,10

MEM_MB_BANK0 9,10

MEM_MB_BANK1 9,10

MEM_MB_BANK2 9,10

MEM_MB_RAS# 9,10

MEM_MB_CAS# 9,10

MEM_MB_WE# 9,10

SC180P50V2JN-1GP

SC1KP50V2KX-1GP

SCD1U10V2KX-4GP

8,10 MEM_MA_BANK0

8,10 MEM_MA_BANK1

8,10 MEM_MA_BANK2

8,10 MEM_MA_RAS#

8,10 MEM_MA_CAS#

8,10 MEM_MA_WE#

MEM_MB_DQS0_P

MEM_MB_DQS0_N

MEM_MB_DQS1_P

MEM_MB_DQS1_N

MEM_MB_DQS2_P

MEM_MB_DQS2_N

MEM_MB_DQS3_P

MEM_MB_DQS3_N

MEM_MB_DQS4_P

MEM_MB_DQS4_N

MEM_MB_DQS5_P

MEM_MB_DQS5_N

MEM_MB_DQS6_P

MEM_MB_DQS6_N

MEM_MB_DQS7_P

MEM_MB_DQS7_N

UMA NODOCK

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_DDR_(2/4)

Size

Document Number

Rev

Date: Friday, April 18, 2008

Olan

Sheet

-1

Plik z chomika:

daro_tt

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