Acer Aspire 8730_Wistron_Big_Bear2_Rev-1.pdf

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Big Bear 2 Block Diagram

Project code: 91.4AV01.001

PCB P/N

: 48.4AV01.

REVISION

-1

PCB STACKUP

SYSTEM DC/DC

TPS51125

INPUTS

OUTPUTS

5V_S5

DCBATOUT

CLK GEN.

RTM875N-606-VD

Mobile CPU

Penryn

4, 5

THERMAL EMC2102

TOP

3D3V_S5

SYSTEM DC/DC

TPS51124

INPUTS

DCBATOUT

1D8V_S3

1D05V_S0

DDR2 DIMM1

667/800 MHz

HOST BUS

667/800MHz

667/800/1067MHz@1.05V

CRT

VCC

GND

OUTPUTS

Cantiga

AGTL+ CPU I/F

DDR Memory I/F

INTEGRATED GRAHPICS

LVDS, CRT I/F

LCD

DDR2 DIMM2

667/800 MHz

HDMI

RT9026

1D8V_S3

DDR_VREF_S0

DDR_VREF_S3

BOTTOM

INT.MIC

Line In

MIC In

www.kythuatvitinh.com

PCIex16

6,7,8,9,10,11

667/800MHz

MXM CONN

RT9018A

1D8V_S3

X4 DMI

400MHz

C-Link0

1D5V_S0

Codec

ICH9M

6 PCIe ports

ACPI 2.0

4 SATA

PCIex1

Giga LAN

ALC888S

AZALIA

BCM5764MKMLG

TXFM

RJ45

G9131

PCI/PCI BRIDGE

PCIex1

New card

PWR SW

G577BR91U

3D3V_S0

2D5V_S0

GFXCORE DC/DC

ISL6263

INPUTS

OUTPUTS

VGFXCORE

0.7~1.25V

12 USB 2.0/1.1 ports

ETHERNET (10/100/1000MbE)

High Definition Audio

LPC I/F

Serial Peripheral I/F

Matrix Storage Technology(DO)

Active Managemnet Technology(DO)

Mini Card

Kedron a/b/g/n

OP AMP

G1431Q

Mini Card

Kedron a/b/g/n

DCBATOUT

LPC BUS

BIOS

MX25L16

W25X16

16M Bits

INT.SPKR

CPU DC/DC

ISL6266A

Line Out

(SPDIF)

OP AMP

G1412

MODEM

MDC Card

19,20,21,22

KBC

WPC775

LPC

DEBUG

CONN

INPUTS

DCBATOUT

OUTPUTS

VCC_CORE_S0

0.35~1.5V

RJ11

USB

SPI

SATA

Blue Tooth

(USB)

Launch

Buttom

CHARGER

BQ24745

OUTPUTS

BT+

DCBATOUT

Camera

(USB)

USB

4 Port

Touch

Pad

Finger

Printer

INT.

CIR

INPUTS

BIOS/DASH

2Mb

1st HDD SATA

2nd HDD SATA

DCBATOUT

SATA

ODD SATA

CardReader

Realtek

RTS5158E

MS/MS Pro/xD

/MMC/SD

5 in 1

UMA

Title

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

BLOCK DIAGRAM

Size

Custom

Document Number

Rev

Big Bear 2

Sheet

-1

Date: Wednesday, October 22, 2008

page 92

ICH9M Functional Strap Definitions

Rev.1.5

ICH9 EDS 642879

Signal

HDA_SDOUT

Usage/When Sampled

XOR Chain Entrance/

PCIE Port Config1 bit1,

Rising Edge of PWROK

Comment

ICH9M Integrated Pull-up

and Pull-down Resistors

ICH9 EDS 642879

Cantiga chipset and ICH9M I/O controller

Hub strapping configuration

Rev.1.5

Pin Name

CFG[2:0]

Montevina Platform Design guide 22339

page 218

Strap Description

FSB Frequency

Select

Configuration

000 = FSB1067

011 = FSB667

010 = FSB800

others = Reserved

0.5

Allows entrance to XOR Chain testing when TP3

pulled low.When TP3 not pulled low at rising edge

of PWROK,sets bit1 of RPC.PC(Config Registers:

offset 224h). This signal has weak internal pull-down

This signal has a weak internal pull-down.

Sets bit0 of RPC.PC(Config Registers:Offset 224h)

This signal has a weak internal pull-up.

Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)

This signal should not be pulled high.

ESI compatible mode is for server platforms only.

This signal should not be pulled low for desttop

and mobile.

Sampled low:Top-Block Swap mode(inverts A16 for

all cycles targeting FWH BIOS space).

Note: Software will not be able to clear the

Top-Swap bit until the system is rebooted

without GNT3# being pulled down.

SIGNAL

CL_CLK[1:0]

CL_DATA[1:0]

CL_RST0#

DPRSLPVR/GPIO16

ENERGY_DETECT

HDA_BIT_CLK

HDA_DOCK_EN#/GPIO33

HDA_RST#

HDA_SDIN[3:0]

HDA_SDOUT

HDA_SYNC

GLAN_DOCK#

GPIO[20]

GNT[3:0]#/GPIO[55,53,51]

Resistor Type/Value

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-DOWN 20K

The pull-up or pull-down active when configured for native

GLAN_DOCK# functionality and determined by LAN controller

HDA_SYNC

GNT2#/

GPIO53

GPIO20

GNT1#/

GPIO51

PCIE config1 bit0,

Rising Edge of PWROK.

PCIE config2 bit2,

Rising Edge of PWROK.

Reserved

ESI Strap (Server Only)

Rising Edge of PWROK

CFG[4:3]

CFG8

CFG[15:14]

CFG[18:17]

CFG5

CFG6

Reserved

DMI x2 Select

iTPM Host

Interface

Intel Management

engine Crypto strap

0 = DMI x2

1 = DMI x4

(Default)

0= The iTPM Host Interface is enabled(Note2)

1=The iTPM Host Interface is disalbed(default)

0 = Transport Layer Security (TLS) cipher

suite with no confidentiality

1 = TLS cipher suite with

confidentiality (default)

0 = Reverse Lanes,15->0,14->1 ect..

1= Normal operation(Default):Lane

Numbered in order

0 = Enable (Note 3)

1= Disabled (default)

GNT3#/

GPIO55

Top-Block

Swap Override.

Rising Edge of PWROK.

CFG7

GNT0#:

SPI_CS1#/

GPIO58

SPI_MOSI

Boot BIOS Destination

Selection 0:1.

Rising Edge of PWROK.

Integrated TPM Enable,

Rising Edge of CLPWROK

GPIO49

DMI Termination Voltage, The signal is required to be low for desktop

Rising Edge of PWROK.

applications and required to be high for

mobile applications.

SATALED#

SPKR

PCI Express Lane

Reversal. Rising Edge

of PWROK.

No Reboot.

Rising Edge of PWROK.

www.kythuatvitinh.com

CFG9

PCIE Graphics Lane

Controllable via Boot BIOS Destination bit

(Config Registers:Offset 3410h:bit 11:10).

GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.

Sample low: the Integrated TPM will be disabled.

Sample high: the MCH TPM enable strap is sampled

low and the TPM Disable bit is clear, the

Integrated TPM will be enable.

PULL-UP 20K

PULL-UP 15K

PULL-UP 20K

PULL-DOWN 20K

CFG10

PCIE Loopback enable

XOR/ALL

GPIO[49]

CFG[13:12]

LDA[3:0]#/FHW[3:0]#

LAN_RXD[2:0]

LDRQ[0]

PME#

Reserve

XOR mode Enabled

ALLZ mode Enabled (Note 3)

Disabled (default)

CFG16

FSB Dynamic ODT

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled (Default)

LDRQ[1]/GPIO23

PWRBTN#

CFG19

DMI Lane Reversal

0 = Normal operation(Default):

Lane Numbered in Order

Signal has weak internal pull-up. Sets bit 27

of MPC.LR(Device 28:Function 0:Offset D8)

SATALED#

If sampled high, the system is strapped to the

"No Reboot" mode(ICH9 will disable the TCO Timer

system reboot feature). The status is readable

via the NO REBOOT bit.

This signal should not be pull low unless using

XOR Chain testing.

Sampled low:the Flash Descriptor Security will be

overridden. If high,the security measures will be

in effect.This should only be enabled in manufacturing

environments using an external pull-up resister.

SPI_CS1#/GPIO58/CLGPIO6

1 = Reverse Lanes

DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)

DMI x2 mode[MCH -> ICH]:(3->0,2->1)

0 = Only Digital Display Port

or PCIE is operational (Default)

1 =Digital display Port and PCIe are

operting simulataneously via the PEG port

0 =No SDVO Card Present (Default)

SPI_MOSI

SPI_MISO

SPKR

TACH_[3:0]

TP[3]

USB[11:0][P,N]

PULL-DOWN 20K

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-DOWN 15K

CFG20

Digital Display Port

(SDVO/DP/iHDMI)

Concurrent with PCIe

TP3

XOR Chain Entrance.

Rising Edge of PWROK.

Flash Descriptor

Security Override Strap

Rising Edge of PWROK

SDVO_CTRLDATA

SDVO Present

1 = SDVO Card Present

0 = LFP Disabled (Default)

Local Flat Panel

(LFP) Present

GPIO33/

HDA_DOCK

_EN#

L_DDC_DATA

1= LFP Card Present; PCIE disabled

SMBus

SMBC_Therm

SMBD_Therm

Media

Board

NOTE:

1. All strap signals are sampled with respect to the leading edge of

the (G)MCH Power OK (PWROK) signal.

2. iTPM can be disabled by a 'Soft-Strap' option in the

Flash-decriptor section of the Firmware. This 'Soft-Strap' is

activated only after enabling iTPM via CFG6.

Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.

Thermal

MXM

USB Table

USB

KBC

BAT_SCL

BAT_SDA

PCIE Routing

LANE1

LANE2

LANE3

LANE4

LANE5

LANE6

LAN MARVELL 88E8071

MiniCard WLAN

MiniCard WWAN/TV

JMB385 Card Reader

NewCard

Pair

Device

USB1

USB4

USB2

USB5(DOCK)

USB3

Bluetooth

MINIC1

WEBCAM

NEW1

MINIC2

SMBC_ICH

BATTERY

CHARGER

ICH9M

SO-DIMM

UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

9LPRS365BKLFT

DDR

Size

Document Number

Reference

Big Bear 2

Sheet

Rev

-1

Date: Wednesday, October 22, 2008

3D3V_S0

R216

1D05V_S0

3D3V_S0

R227

3D3V_CLKGEN_S0

3D3V_48MPWR_S0

R218

1D05V_CLKPLL_S0

C316

SC1U16V3ZY-GP

3D3V_S0

CLK48_ICH

C312

Do Not Stuff

C322

SCD1U16V2ZY-2GP

C314

SC4D7U10V5ZY-3GP

C329

SCD1U16V2ZY-2GP

C330

SCD1U16V2ZY-2GP

C318

SCD1U16V2ZY-2GP

C325

SC4D7U10V5ZY-3GP

C311

SCD1U16V2ZY-2GP

C321

SCD1U16V2ZY-2GP

C323

SCD1U16V2ZY-2GP

Do Not Stuff

C309

Do Not Stuff

C310

SCD1U16V2ZY-2GP

Do Not Stuff

C331

SCD1U16V2ZY-2GP

C301

Do Not Stuff

C306

EMI

EC44

Do Not Stuff

RN51

SRN10KJ-6-GP

RN50

SATACLKREQ#

CLK_MCH_OE#

LAN_CLKREQ#

MXM_CLKREQ#

3D3V_CLKGEN_S0

1D05V_CLKPLL_S0

3D3V_48MPWR_S0

PCLKCLK0

PCLKCLK1

CR#_H

CR#_G

SRN470J-3-GP

U13

VDDREF

VDD48

VDDPCI

VDDSRC

VDDCPU

VDDPLL3

C328

SC33P50V2JN-3GP

VDD96_IO

VDDPLL3_IO

VDDSRC_IO

VDDCPU_IO

CL=20pF±0.2pF

www.kythuatvitinh.com

GEN_XTAL_IN

CPUT0

CPUC0

CLK_CPU_BCLK 4

CLK_CPU_BCLK# 4

CPU

82.30005.891

82.30005.951

C324

R226

Do Not Stuff

GEN_XTAL_OUT

X-14D31818M-35GP

CPUT1_F

CPUC1_F

CLK_MCH_BCLK 6

CLK_MCH_BCLK# 6

CLK_PCIE_ICH 20

CLK_PCIE_ICH# 20

RN46

SRN33J-5-GP-U

GEN_XTAL_OUT_R

CLK48_CR

CLK48_ICH

CLK48

CPUT2_ITP/SRCT8

CPUC2_ITP/SRCC8

SRCT7/CR#_F

SRCC7/CR#_E

SRCT6

SRCC6

SB DMI

USB_48MHZ/FSLA

SC33P50V2JN-3GP

4,7

CPU_SEL0

R221

2K2R2J-2-GP

20 PM_STPPCI#

20 PM_STPCPU#

CLK_PCIE_NEW 31

CLK_PCIE_NEW# 31

New Card

PCI_STOP#

CPU_STOP#

CLK_PCIE_MINI1 32

CLK_PCIE_MINI1# 32

CLK_PCIE_LAN 28

CLK_PCIE_LAN# 28

WirelessLAN

LAN

3D3V_S0

RN49

3D3V_S0

PCLKCLK2

PCLKCLK4

PCLKCLK5

CPU_SEL2_R

12,13,22 SMBC_ICH

12,13,22 SMBD_ICH

SCLK

SDATA

SRCT10

SRCC10

R228

20 CLK_PWRGD

Do Not Stuff

PCLKCLK0

PCLKCLK1

PCLKCLK2

PCLKCLK3

PCLKCLK4

PCLKCLK5

CPU_SEL2_R

CK_PWRGD/PD#

SRCT11/CR#_H

SRCC11/CR#_G

SRCT9

SRCC9

CR#_H

CR#_G

DREFSSCLK_1

DREFSSCLK#_1

DREFCLK_1

DREFCLK#_1

SRN10KJ-6-GP

4,7

CPU_SEL2

PCLK_FWH

PCLK_KBC

PCLK_ICH

CLK_ICH14

RN48

CLK48_CR

SRN33J-7-GP

CLK_PCIE_PEG 30

CLK_PCIE_PEG# 30

CLK_MCH_3GPLL 7

CLK_MCH_3GPLL# 7

CLK_PCIE_MINI2 32

CLK_PCIE_MINI2# 32

CLK_PCIE_SATA 19

CLK_PCIE_SATA# 19

MXM

NB CLK

SB SATA

NB CLK

(96 MHz)

PCI0/CR#_A

PCI1/CR#_B

PCI2/TME

PCI3

PCI4/27_SELECT

PCI_F5/ITP_EN

SRCT4

SRCC4

SRCT3/CR#_C

SRCC3/CR#_D

SRCT2/SATAT

SRCC2/SATAC

EMI

EC43

Do Not Stuff

4,7

CPU_SEL1

CLK_PWRGD

CPU_SEL2_R

FSLB/TEST_MODE

REF0/FSLC/TEST_SEL

NC#55

GND

GNDSRC

GNDCPU

GND

GND48

GNDPCI

GNDREF

27MHZ_NONSS/SRCT1/SE1

27MHZ_SS/SRCC1/SE2

SRCT0/DOTT_96

SRCC0/DOTC_96

UMA

RN44

SRN0J-6-GP

RN45

SRN0J-6-GP

EMI

DREFSSCLK 7

DREFSSCLK# 7

DREFCLK 7

DREFCLK# 7

EC111

Do Not Stuff

GND

UMA

ICS9LPRS365BKLFT setting table

PIN NAME

DESCRIPTION

PCI0/CR#_A

Byte 5, bit 7

0 = PCI0 enabled (default)

1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair

Byte 5, bit 6

0 = CR#_A controls SRC0 pair (default),

1= CR#_A controls SRC2 pair

Byte 5, bit 5

0 = PCI1 enabled (default)

1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair

Byte 5, bit 4

0 = CR#_B controls SRC1 pair (default)

1= CR#_B controls SRC4 pair

0 = Overclocking of CPU and SRC Allowed

1 = Overclocking of CPU and SRC NOT allowed

3.3V PCI clock output

71.09365.A03

71.00875.C03

RTM875N-606-VD-GRT-GP

ICS9LPRS365BKLFT-GP-U

SEL2 SEL1 SEL0

FSC FSB FSA

PIN NAME

SRCC3/CR#_D

SRCC7/CR#_E

DESCRIPTION

Byte 5, bit 1

0 = SRC3 enabled (default)

1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair

Byte 5, bit 0

0 = CR#_D controls SRC1 pair (default)

1= CR#_D controls SRC4 pair

Byte 6, bit 7

0 = SRC7# enabled (default)

1= CR#_F controls SRC6

Byte 6, bit 6

0 = SRC7 enabled (default)

1= CR#_F controls SRC8

Byte 6, bit 5

0 = SRC11# enabled (default)

1= CR#_G controls SRC9

Title

Byte 6, bit 4

0 = SRC11 enabled (default)

1= CR#_H controls SRC10

UMA

CPU

100M

133M

166M

200M

266M

FSB

533M

667M

800M

1066M

PCI1/CR#_B

PCI2/TME

PCI3

PCI4/27M_SEL

PCI_F5/ITP_EN

SRCT3/CR#_C

0 = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as DOT96#

1 = Pin24 as 27MHz, Pin25 as 27MHz_SS, Pin20 as SRC-0, Pin21 as SRC-0#

0 =SRC8/SRC8#

1 = ITP/ITP#

Byte 5, bit 3

0 = SRC3 enabled (default)

1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair

Byte 5, bit 2

0 = CR#_C controls SRC0 pair (default),

1= CR#_C controls SRC2 pair

SRCT7/CR#_F

SRCC11/CR#_G

SRCT11/CR#_H

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Size

Document Number

Clock Generator

Big Bear 2

Sheet

Rev

-1

Date: Wednesday, October 22, 2008

H_A#[35..3]

H_DINV#[3..0]

H_DSTBN#[3..0]

CPU1A

1 OF 4

H_A#3

H_A#4

H_A#5

H_A#6

H_A#7

H_A#8

H_A#9

H_A#10

H_A#11

H_A#12

H_A#13

H_A#14

H_A#15

H_A#16

TP274

Do Not Stuff

Place testpoint on

H_IERR# with a GND

0.1" away

H_DSTBP#[3..0]

H_D#[63..0]

H_DINV#[3..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]

H_D#[63..0]

H_ADSTB#0

H_REQ#[4..0]

Side Band

Non GTL

www.kythuatvitinh.com

H_A#17

H_A#18

H_A#19

H_A#20

H_A#21

H_A#22

H_A#23

H_A#24

H_A#25

H_A#26

H_A#27

H_A#28

H_A#29

H_A#30

H_A#31

H_A#32

H_A#33

H_A#34

H_A#35

H_ADSTB#1

H_A20M#

H_FERR#

H_IGNNE#

H_STPCLK#

H_INTR

H_NMI

H_SMI#

AA4

AB2

AA3

D22

A17#

A18#

A19#

A20#

A21#

A22#

A23#

A24#

A25#

A26#

A27#

A28#

A29#

A30#

A31#

A32#

A33#

A34#

A35#

ADSTB1#

A20M#

FERR#

IGNNE#

STPCLK#

LINT0

LINT1

SMI#

HIT#

HITM#

XDP/ITP SIGNALS

BPM0#

BPM1#

BPM2#

BPM3#

PRDY#

PREQ#

TCK

TDI

TDO

TMS

TRST#

DBR#

AD4

AD3

AD1

AC4

AC2

AC1

AC5

AA6

AB3

AB5

AB6

C20

XDP_BPM#0

XDP_BPM#1

XDP_BPM#2

XDP_BPM#3

XDP_BPM#4

XDP_BPM#5

XDP_TCK

XDP_TDI

XDP_TDO

XDP_TMS

XDP_TRST#

XDP_DBRESET#

TP272

TP18

TP21

TP19

TP20

TP22

TP17

TP273

TP23

TP24

TP271

TP29

Do Not Stuff

H_HIT#

H_HITM#

H_THERMDA

H_THERMDC

C74

Do Not Stuff

DATA GRP2

H_REQ#0

H_REQ#1

H_REQ#2

H_REQ#3

H_REQ#4

REQ0#

REQ1#

REQ2#

REQ3#

REQ4#

RESET#

RS0#

RS1#

RS2#

TRDY#

H_RS#0

H_RS#1

H_RS#2

CPU_PROCHOT#

A3#

A4#

A5#

A6#

A7#

A8#

A9#

A10#

A11#

A12#

A13#

A14#

A15#

A16#

ADSTB0#

ADS#

BNR#

BPRI#

F21

D20

H_ADS#

H_BNR#

H_BPRI#

THERMTRIP#

PM_THRMTRIP-A# 7,19,40

HCLK

BCLK0

BCLK1

A22

A21

CLK_CPU_BCLK 3

CLK_CPU_BCLK# 3

PM_THRMTRIP#

should connect to

ICH9 and MCH

without T-ing

( No stub)

Layout Note:

"CPU_GTLREF0"

0.5" max length.

1D05V_S0

RSVD#M4

RSVD#N5

RSVD#T2

RSVD#V3

RSVD#B2

RSVD#C3

RSVD#D2

RSVD#D22

RSVD#D3

RSVD#F6

KEY_NC

DATA GRP3

ADDR GROUP 0

ADDR GROUP 1

CONTROL

DEFER#

DRDY#

DBSY#

BR0#

IERR#

INIT#

LOCK#

H_DEFER# 6

H_DRDY# 6

H_DBSY# 6

H_BREQ#0 6

H_IERR#

H_INIT#

TP27 Do Not Stuff

1D05V_S0

RN8

SRN56J-4-GP

CPU1B

2 OF 4

H_IERR#

H_D#0

H_D#1

H_D#2

H_D#3

H_D#4

H_D#5

H_D#6

H_D#7

H_D#8

H_D#9

H_D#10

H_D#11

H_D#12

H_D#13

H_D#14

H_D#15

H_LOCK# 6

H_CPURST# 6,39

H_RS#[2..0]

H_TRDY# 6

H_DSTBN#0

H_DSTBP#0

H_DINV#0

E22

F24

E26

G22

F23

G25

E25

E23

K24

G24

J24

J23

H22

F26

K22

H23

J26

H26

H25

D0#

D1#

D2#

D3#

D4#

D5#

D6#

D7#

D8#

D9#

D10#

D11#

D12#

D13#

D14#

D15#

DSTBN0#

DSTBP0#

DINV0#

D16#

D17#

D18#

D19#

D20#

D21#

D22#

D23#

D24#

D25#

D26#

D27#

D28#

D29#

D30#

D31#

DSTBN1#

DSTBP1#

DINV1#

GTLREF

TEST1

TEST2

TEST3

TEST4

TEST5

TEST6

BSEL0

BSEL1

BSEL2

D32#

D33#

D34#

D35#

D36#

D37#

D38#

D39#

D40#

D41#

D42#

D43#

D44#

D45#

D46#

D47#

DSTBN2#

DSTBP2#

DINV2#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#

DSTBN3#

DSTBP3#

DINV3#

Y22

AB24

V24

V26

V23

T22

U25

U23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

Y26

AA26

U22

H_D#32

H_D#33

H_D#34

H_D#35

H_D#36

H_D#37

H_D#38

H_D#39

H_D#40

H_D#41

H_D#42

H_D#43

H_D#44

H_D#45

H_D#46

H_D#47

DATA GRP0

H_DSTBN#2 6

H_DSTBP#2 6

H_DINV#2 6

THERMAL

PROCHOT#

THRMDA

THRMDC

D21

A24

B25

CPU_PROCHOT#

H_THERMDA 23

H_THERMDC 23

R73

Do Not Stuff

CPU_PROCHOT#_R

RESERVED

R64

1KR2F-3-GP

H_DSTBN#1

H_DSTBP#1

H_DINV#1

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L23

H_D#21

M24

H_D#22

L22

H_D#23

M23

H_D#24

P25

H_D#25

P23

H_D#26

P22

H_D#27

T24

H_D#28

R24

H_D#29

L25

H_D#30

T25

H_D#31

N25

L26

M26

N24

AE24

AD24

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

AC22

AD23

AF22

AC23

AE25

AF24

AC20

R26

U26

AA1

D24

AE6

H_D#48

H_D#49

H_D#50

H_D#51

H_D#52

H_D#53

H_D#54

H_D#55

H_D#56

H_D#57

H_D#58

H_D#59

H_D#60

H_D#61

H_D#62

H_D#63

DATA GRP1

BGA479-SKT6-GPU7

62.10079.001

62.10053.401

1D05V_S0

ICH

H_DSTBN#3 6

H_DSTBP#3 6

H_DINV#3 6

COMP0

COMP1

COMP2

COMP3

R70

R69

R66

R68

CPU_GTLREF0

Do Not Stuff

TP28

C48

Do Not Stuff

TP144

Do Not Stuff

TP148

3,7

CPU_SEL0

CPU_SEL1

CPU_SEL2

R63

2KR2F-3-GP

AD26

TEST1

C23

TEST2

D25

RSVD_CPU_12

C24

TEST4

AF26

RSVD_CPU_13

AF1

RSVD_CPU_14

A26

B22

B23

C21

MISC

COMP0

COMP1

COMP2

COMP3

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

27D4R2F-L1-GP

54D9R2F-L1-GP

27D4R2F-L1-GP

54D9R2F-L1-GP

H_DPRSTP# 7,19,42

H_DPSLP# 19

H_DPWR# 6

H_PWRGD 19,39,40

H_CPUSLP# 6

PSI#

BGA479-SKT6-GPU7

62.10079.001

62.10053.401

RN3

XDP_TDI

XDP_TMS

XDP_BPM#5

Follow Demo Circuit

SRN56J-5-GP

H_CPURST#

R71

R75

R72

C43

TEST1

Do Not Stuff

TEST2

Do Not Stuff

Net "TEST4" as short as possible,

make sure "TEST4" routing is

reference to GND and away other

noisy signals

Layout Note:

Comp0, 2 connect with Zo=27.4 ohm, make

trace length shorter than 0.5" .

Comp1, 3 connect with Zo=55 ohm, make

trace length shorter than 0.5" .

Do Not Stuff

RN2

TEST4

Do Not Stuff

XDP_TCK

XDP_TRST#

SRN56J-4-GP

3D3V_S0

UMA

All place within 2" to CPU

XDP_DBRESET#

R74

Do Not Stuff

1D05V_S0

Title

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

XDP_TDO

R65

Do Not Stuff

Size

Document Number

CPU (1 of 2)

Big Bear 2

Sheet

Rev

-1

Date: Wednesday, October 22, 2008

VCC_CORE

CPU1D

4 OF 4

VCC_CORE

C53

Do Not Stuff

C45

Do Not Stuff

C68

Do Not Stuff

CPU1C

3 OF 4

C71

Do Not Stuff

A10

A12

A13

A15

A17

A18

A20

B10

B12

B14

B15

B17

B18

B20

C10

C12

C13

C15

C17

C18

D10

D12

D14

D15

D17

D18

E10

E12

E13

E15

E17

E18

E20

F10

F12

F14

F15

F17

F18

F20

AA7

AA9

AA10

AA12

AA13

AA15

AA17

AA18

AA20

AB9

AC10

AB10

AB12

AB14

AB15

AB17

AB18

www.kythuatvitinh.com

SC10U6D3V5MX-3GP

Do Not Stuff

VCC

VCCP

VCCA

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VCCSENSE

VSSSENSE

G21

J21

K21

M21

N21

R21

T21

V21

W21

B26

C26

AD6

AF5

AE5

AF4

AE3

AF3

AE2

AF7

AE7

VCCP_1D05

Do Not Stuff

C56

SCD1U10V2KX-4GP

C61

SCD1U16V2KX-3GP

layout note: "1D5V_VCCA_S0"

as short as possible

1D5V_S0

1D5V_VCCA_S0

L11

H_VID0

H_VID1

H_VID2

H_VID3

H_VID4

H_VID5

H_VID6

H_VID[6..0]

VCC_CORE

C418

SCD01U16V2KX-3GP

C420

SC10U6D3V5MX-3GP

HCB1608KF121T30-GP

68.00230.041

68.00206.021

AB20

AB7

AC7

AC9

AC12

AC13

AC15

AC17

AC18

AD7

AD9

AD10

AD12

AD14

AD15

AD17

AD18

AE9

AE10

AE12

AE13

AE15

AE17

AE18

AE20

AF9

AF10

AF12

AF14

AF15

AF17

AF18

AF20

TC1

ST900U2D5VM-1-GP

77.E9071.011

NEC

TP146

Do Not Stuff

VCC_CORE

C469

C464

C47

C46

C467

C52

C466

C51

C465

1D05V_S0

C64

SCD1U10V2KX-4GP

C59

Do Not Stuff

C62

Do Not Stuff

C58

1D05V_S0

C60

SCD1U16V2KX-3GP

C57

SCD1U16V2KX-3GP

R60

100R2F-L1-GP-U

VCC_SENSE 42

VSS_SENSE 42

BGA479-SKT6-GPU7

62.10079.001

62.10053.401

R62

100R2F-L1-GP-U

Layout Note:

VCCSENSE and VSSSENSE lines

should be of equal length.

A11

A14

A16

A19

A23

AF2

B11

B13

B16

B19

B21

B24

C11

C14

C16

C19

C22

C25

D11

D13

D16

D19

D23

D26

E11

E14

E16

E19

E21

E24

F11

F13

F16

F19

F22

F25

G23

G26

H21

H24

J22

J25

K23

K26

L21

L24

M22

M25

N23

N26

VSS

P21

P24

R22

R25

T23

T26

U21

U24

V22

V25

W23

W26

Y21

Y24

AA2

AA5

AA8

AA11

AA14

AA16

AA19

AA22

AA25

AB1

AB4

AB8

AB11

AB13

AB16

AB19

AB23

AB26

AC3

AC6

AC8

AC11

AC14

AC16

AC19

AC21

AC24

AD2

AD5

AD8

AD11

AD13

AD16

AD19

AD22

AD25

AE1

AE4

AE8

AE11

AE14

AE16

AE19

AE23

AE26

AF6

AF8

AF11

AF13

AF16

AF19

AF21

A25

AF25

Do Not Stuff

TP145

Do Not Stuff

TP147

TP155

Do Not Stuff

TP149

Do Not Stuff

Layout Note:

Provide a test point (with

no stub) to connect a

differential probe

between VCCSENSE and

VSSSENSE at the location

where the two 54.9ohm

resistors terminate the

55 ohm transmission line.

BGA479-SKT6-GPU7

62.10079.001

62.10053.401

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size

Document Number

CPU (2 of 2)

Big Bear 2

Sheet

Rev

-1

Date: Wednesday, October 22, 2008

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