Acer Aspire 7551_Wistron_JE70-DN_SJV71-DN_HM72-DN_Rev-1.pdf

(2694 KB) Pobierz
5
4
3
2
1
Project code: 91.4HP01.001
PCB P/N
: 48.4HP01.011
REVISION
: 09929-1
DDR3
D
PCB STACKUP
800/1066/1333MHz
SYSTEM DC/DC
RT8223
INPUTS
DCBATOUT
DIMM1
16
800/1066/1333MHz
AMD Champlain CPU
S1G4 (45W)
638-Pin uFCPGA638
4,5,6,7
TOP
CRT
LCD
20
19
21
VCC
S
S
GND
BOTTOM
45
OUTPUTS
5V_S5(5A)
3D3V_S5(5A)
D
DDR3
800/1066/1333MHz
800/1066/1333 MHz
DIMM2 & DIMM3
17
SYSTEM DC/DC
RT8209E
INPUTS
DCBATOUT
OUT
HT 3.0
16X16
HDMI
Madison & Park
46
OUTPUTS
1D5V_S3
IN
CLK GEN.
3
North Bridge
AMD RS880M
CPU I/F
LVDS, CRT I/F
INTEGRATED GRAHPICS
16X
PCI EXPRESS GRAPHIC
ICS9LPRS480BKLFT
71.09480.A03
RTM880N-796-VB-GRT 71.00880.A03
C
ATI
52,53,54,55,56
57, 58, 59, 60
DDR3
VRAM
SYSTEM DC/DC
RT8015A
INPUTS
DCBATOUT
47
OUTPUTS
1D8V_S0
PCIex1
LAN
Giga LAN
BCM57780
26
TXFM
27
RJ45
27
RT9025
5V_S5
1D05V_S0
48
C
21*21*1.84mm
INT MIC
30
8,9,10
Mini Card
MIC In
RT9161
3D3V_S0
2D5V_S0
(200mA)
48
Codec
ALC272
28
AZALIA
A-Link
4X1
WLAN
33
33
Mini Card
RT9025
3D3V_S0
1V_VGA
(1.2A)
48
30
Line Out
30
South Bridge
AMD SB820
USB 2.0/1.1 ports
ETHERNET (10/100/1000Mb)
High Definition Audio
ATA 66/100
ACPI 1.1
LPC I/F
LPC BUS
BIOS
MXIC
MX25L1605
RT9025,RT8209E
47
3D3V_S5
5V_S5
1D1V_S5
1D1V_S0
KBC
Novoton
NPCE781B
36
LPC
DEBUG
37
CONN.
CHARGER
BQ24745
INPUTS
49
OUTPUTS
CHG_PWR
18V
DCBATOUT
6.0A
100mA
B
37
B
INT.SPKR
30
OP AMP
29
PCI/PCI BRIDGE
23*23*1.92mm
11,12,13,14,15
Touch
Pad
38
CardReader
AU6437
INT.
KB
36
UP+5V
Daughter Board
Power Board(09744-1)
Daughter Board
Power Board(09741-1)
Daughter Board
Power Board(09742-1)
5V
CPU DC/DC
ISL6265HR
44
INPUTS OUTPUTS
VCC_CORE_S0_0
0~1.55V
DCBATOUT
0~1.55V
18A
18A
18A
MS/MS Pro/xD
/MMC/SD
5 in 1
SATA
HDD SATA
22
USB
USB
2 Port
Blue Tooth
24
32
32
VCC_CORE_S0_1
VDDNB
0~1.55V
SATA
ODD SATA
A
25
Daughter Board
USB Board
23
Camera
19
JE70-DN
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
USB
1 Port
25
Size
BLOCK DIAGRAM
Document Number
W ednesday, March 31, 2010
Rev
A3
Date:
5
4
3
2
JE70-DN
SB
Sheet
1
1
of
63
5
4
3
2
1
page36
EC Functional Strap Definitions
Signal
Comment
Test Mode Select. Sampled at VCC Power-Up reset or VCC_POR Input reset, to
determine the device operation mode as follows:
page9
STRAP_DEBUG_BUS_GPIO_ENABLEb
D
TEST#
pin110
No pull-down resistor: Normal operation mode (XORTR and TRIST strap pins
are ignored).
10 K external pull-down resistor:Test mode (ICT or XOR-Tree Test mode,
according to XORTR and TRIST strap pins).
XOR-Tree Mode Select. Sampled at VCC Power-Up reset or VCC_POR Input reset, to
select the XOR-Tree Test mode, if TEST is strapped low:
D
*
Enables the Test Debug Bus using GPIO.(PIN: RS780M--> VSYNC#)
1 :Disable
0 : Enable
RS780: Enables Side port memory ( RS880 use HSYNC#)
XORTR#
pin111
No pull-down resistor: Not allowed if TEST pin is strapped low.
10 K external pull-down resistor:XOR-Tree Test mode .Note: TRIST strap
pin must be left unconnected.
ICT Mode Select. Sampled at VCC Power-Up reset or VCC_POR Input reset, to
select the ICT Test mode, if TEST is strapped low:
No pull-down resistor: Not allowed if TEST pin is strapped low.
*
1
:Disable
0 : Enable
Selects Loading of STRAPS From EEPROM
*
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected,
or use default values if not connected
SUS_STAT#
TRIST#
pin112
10 K external pull-down resistor:ICT Test mode (see Section 3.4.1 on page
53), forces the device to float its output and I/O pins.Note: XORTR strap pin
must be left unconnected.
JTAG Select. Sampled at VCC Power-Up reset or VCC_POR Input reset, to select
the JTAG signals to device pins (see Table 4 on page 35 for details).
JEN0#, JENK#
Both JEN0 and JENK, are pulled to 1 by an internal resistor
pin49,53
The external 10 K
pull-down resistor must be connected to GND.
page15
C
PCI_AD27
PULL
HIGH
USE PCI
PLL
DEFAULT
PCI_AD26
DISABLE ILA
AUTORUN
DEFAULT
PCI_AD25
USE FC
PLL
DEFAULT
PCI_AD24
USE DEFAULT
PCIE STRAPS
DEFAULT
PCI_AD23
DISABLE PCI
MEM BOOT
DEFAULT
SHBM
pin83
Shared Host BIOS Memory. Sampled at VCC Power-Up reset or VCC_POR Input
reset, to determine the state of the shared BIOS memory.
No pull-down resistor:Disable the shared BIOS memory.
10 K
external pull-down resistor:Enable the shared BIOS memory
C
SDP_VIS#
Port80 (SDP) Visibility Mode Select. Sampled at VCC Power-Up reset or
VCC_POR Input reset, to select the Visibility mode for the Port80 (SDP).
No pull-down resistor: SDP in Normal mode
PULL
LOW
BYPASS
PCI PLL
ENABLE ILA
AUTORUN
BYPASS FC
PLL
USE EEPROM
PCIE STRAPS
ENABLE PCI
MEM BOOT
pin41
10 K
XOR_OUT
pin35
external pull-down resistor:SDP in Visibility mode.
XOR-Tree Output. The device pins are internally connected in a XOR-tree structure
Note: SB820 has 15K internal PU FOR PCI_AD[27:23]
page15
PCI_CLK1
B
page12
PCI_CLK2
Watchdog
Timer
Enabled
USB
Pair
12
11
10
9
8
7
6
Device
MINI2 CARD
NC
NC
CCD
NC
Bluetooth
USB3
USB2
CardReader
NC
USB4
MINI1 CARD
USB1
JE70-DN
B
PCI_CLK3
USE
DEBUG
STRAP
PCI_CLK4
non_Fusion
CLOCK MODE
DEFAULT
LPC_CLK0
EC
ENABLED
LPC_CLK1
CLKGEN
ENABLED
DEFAULT
AZ_SDOUT
LOW POWER
MODE
GPIO200
GPIO199
PULL
HIGH
ALLOW
PCIE Gen2
DEFAULT
H,H = Reserved
H,L = SPI ROM
PULL
LOW
FORCE
PCIE Gen1
Watchdog
Timer
Disabled
DEFAULT
IGNORE
DEBUG
STRAP
DEFAULT
FUSION
CLOCK MODE
EC
DISABLED
DEFAULT
CLKGEN
DISABLED
PERFORMANCE
MODE
DEFAULT
L,H = LPC ROM (Default)
L,L = FWH ROM
OCP3#
5
4
3
NOTE: SB820 HAS INTERNAL 15K PULL UP RESISTOR FOR RTCCLK
OCP2#
OCP0#
2
1
0
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
A
Reference
Size
Document Number
Thursday, November 19, 2009
Rev
A3
Date:
JE70-DN
SB
Sheet
2
of
63
1
5
4
3
2
5
4
3
2
1
3D3V_S0
3D3V_CLK_VDD
1
1
1
1
1
1
1
1
1
2R3J-GP
C840
SC4D7U6D3V3KX-GP
1
2
C808
SC10U10V5ZY-1GP
C809
SC10U10V5ZY-1GP
C519
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C814
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C825
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C817
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C512
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C812
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
1
R556
2
0R0603-PAD
DY
DY
C517
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
3D3V_S0
R603
1
2
3D3V_48MPW R_S0
C838
SC1U10V2KX-1GP
DY
2
2
2
2
2
2
2
2
2
3000mA.80ohm
D
2
D
CLK_PCIE_PEG
CLK_PCIE_PEG#
C830
CLK_NB_GFX
CLK_NB_GFX#
CLK_PCIE_SB
C833
CLK_PCIE_SB#
SC12P50V2JN-L1-GP
CLK_PCIE_LAN
1
2
SC22P50V2JN-4GP
DY
3D3V_S0
1D1V_CLK_VDDIO
R591
DY
EC62
DY
1
EC63
1
EC65
1
EC64
1
2
SC22P50V2JN-4GP
2
SC22P50V2JN-4GP
1
1
1
1
1
1
10MR2J-L-GP
U75
1D1V_CLK_VDDIO
GEN_XTAL_IN
GEN_XTAL_OUT
82.30005.A51
X-14D31818M-50GP
1
C816
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C820
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C518
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C813
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C516
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C815
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
1
R565
2
0R0603-PAD
1
3D3V_CLK_VDD
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C515
DY
2
SC12P50V2JN-L1-GP
1
X7
DY
DY
2
2
SC22P50V2JN-4GP
2
2
2
2
2
2
2
2
SC22P50V2JN-4GP
DY
EC69
DY
1
EC68
1
2
26
25
48
47
16
17
11
VDDATIG
VDDATIG_IO
VDDCPU
VDDCPU_IO
VDDSRC
VDDSRC_IO
VDDSRC_IO
VDDSB_SRC
VDDSB_SRC_IO
VDDSATA
VDD
VDDHTT
VDDREF
VDD48
PD#
X1
X2
SMBCLK
SMBDAT
ATIG0T_LPRS
ATIG0C_LPRS
ATIG1T_LPRS
ATIG1C_LPRS
CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#
CPUKG0T_LPRS
CPUKG0C_LPRS
61
62
2
3
30
29
28
27
23
45
44
39
38
50
49
64
59
58
57
2
1
2
SC22P50V2JN-4GP
2
SC22P50V2JN-4GP
SMBC0_SB 12,16,17
SMBD0_SB 12,16,17
CLK_PCIE_LAN#
CLK_NB_GPPSB
CLK_NB_GPPSB#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
DY
EC67
DY
1
EC66
1
2
SC22P50V2JN-4GP
DY
3D3V_CLK_VDD
35
34
C
CLK_PCIE_PEG 52
CLK_PCIE_PEG# 52
CLK_NB_GFX 9
CLK_NB_GFX# 9
CLKREQ0#
LAN_CLKREQ#
CLKREQ2#
W LAN_CLKREQ#
MIN2_CLKREQ#
TP168 TPAD14-GP
LAN_CLKREQ# 26
TP166 TPAD14-GP
W LAN_CLKREQ# 33
MIN2_CLKREQ# 33
CPU_CLK
CPU_CLK#
CLK_48
REF0
REF1
REF2
R602
1
6
6
2
SC22P50V2JN-4GP
DY
EC71
DY
DY
DY
1
EC70
1
EC73
1
EC72
1
2
SC22P50V2JN-4GP
1
R303
2
0R0603-PAD
C826
SC1U10V2KX-1GP
2
VDD_REF
3D3V_48MPW R_S0
PD#
40
4
55
56
63
51
22
21
20
19
15
14
13
12
9
8
42
41
6
5
2
SC22P50V2JN-4GP
C
1
2
SC22P50V2JN-4GP
2
SC22P50V2JN-4GP
DY
EC76
DY
1
EC77
1
2
SB A-Link
LAN
NB A-Link
MINI1
MINI2
11 CLK_PCIE_SB
11 CLK_PCIE_SB#
26 CLK_PCIE_LAN
26 CLK_PCIE_LAN#
9 CLK_NB_GPPSB
9 CLK_NB_GPPSB#
33 CLK_PCIE_MINI1
33 CLK_PCIE_MINI1#
33 CLK_PCIE_MINI2
33 CLK_PCIE_MINI2#
SC22P50V2JN-4GP
53 OSC_SPREAD
53 CLK_27M_VGA
B
R608
1
22R2J-2-GP
2
0R0402-PAD
CLK_SRC0T_LPRS
CLK_SRC0C_LPRS
DY
2
1
1
R607
37
36
32
31
54
53
53 JTAG_TCK
R615
1K2R2F-1-GP
DY
2
9 CLK_NBHT_CLK
9 CLK_NBHT_CLK#
R606
2
ATI_ES
1026
0R2J-2-GP
R579
1
0R0402-PAD
2
R577
1
0R0402-PAD
2
add R904
CLK_NBHT_CLK_1
CLK_NBHT_CLK#_1
SRC0T_LPRS
SRC0C_LPRS
48MHZ_0
SRC1T_LPRS
SRC1C_LPRS
SRC2T_LPRS
REF0/SEL_HTT66
SRC2C_LPRS
REF1/SEL_SATA
SRC3T_LPRS
REF2/SEL_27
SRC3C_LPRS
SRC4T_LPRS
SRC4C_LPRS
SRC6T/SATAT_LPRS
GNDSATA
SRC6C/SATAC_LPRS
GNDATIG
SRC7T_LPRS/27MHZ_SS
GND
SRC7C_LPRS/27MHZ_NS
GNDHTT
GNDREF
GNDCPU
SB_SRC0T_LPRS
GND48
SB_SRC0C_LPRS
SB_SRC1T_LPRS
GNDSRC
SB_SRC1C_LPRS
GNDSRC
GNDSB_SRC
HTT0T_LPRS/66M
HTT0C_LPRS/66M
ICS9LPRS480BKLFT-GP
CPU_CLK
CPU_CLK#
CLK_NBHT_CLK
2
SC22P50V2JN-4GP
2
22R2J-2-GP
CLK48_USB 12
DY
EC75
DY
1
EC74
1
2
SC22P50V2JN-4GP
2
SC22P50V2JN-4GP
1
EC59
CLK_NBHT_CLK#
CLK_27M_VGA
DY
EC79
DY
DY
1
EC78
1
EC80
2
DY
43
24
7
52
60
46
1
10
18
33
65
2
SC22P50V2JN-4GP
SC22P50V2JN-4GP
2
SC22P50V2JN-4GP
SB_1224
EMI
B
1
NB CLOCK INPUT TABLE
NB CLOCKS
RS880
100M DIFF
HT_REFCLKN
100M DIFF
CLK_SB_14M 11,12
REFCLK_P
14M SE (1.1V)
REFCLK_N
GFX_REFCLK
GPP_REFCLK
GPPSB_REFCLK
vref
100M DIFF(IN/OUT)*
NC
GND
NB HT
71.09480.A03
2ND = 71.00880.A03
REF1
3D3V_S5
3D3V_S0
RN77
3D3V_S0
1105 modify R229
R301
HT_REFCLKP
1
2
33R2F-3-GP
DY
R572
R299
3D3V_S0
8
7
6
5
1
2
3
4
PD#
LAN_CLKREQ#
W LAN_CLKREQ#
RUNPW ROK_D
RUNPW ROK_D
2
1
MIN2_CLKREQ#
1
75R2F-2-GP
2
41
10KR2J-3-GP
DY
100M DIFF
SRN10KJ-6-GP
2
2
DY
R308
10KR2J-3-GP
DY
R302
10KR2J-3-GP
2
R587
10KR2J-3-GP
SEL_27
REF2
1*
0
27MHz non-spreading singled clock on pin 5
and 27MHz spread clock on pin 6
100MHz differential spreading SRC clock
100MHz non-spreading differential SATA clock
100MHz differential spreading SRC clock
66MHz 3.3V single ended HTT clock
100MHz differential HTT clock
R310
REF0
2
2
1
1
1
1
158R2F-GP
R309
1
CLK_NB_14M 9
A
REF0
REF1
REF2
SEL_SATA
REF1
SEL_HTT66
REF0
1
0*
1
0*
90D9R2F-1-GP
JE70-DN
A
2
2
DY
R582
10KR2J-3-GP
2
R307
10KR2J-3-GP
R306
10KR2J-3-GP
CPU_CLK(200MHz)
OSC_14M_NB
RS880M 1.1V 158R/90.9R
Title
Size
Document Number
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1
1
1
CLKGEN_ICS9LPRS480
Rev
A3
Date:
5
4
3
2
JE70-DN
Monday, March 01, 2010
Sheet
1
SB
3
of
63
5
4
3
2
1
D
D
1D1V_S0
Place close to socket
SC10U6D3V3MX-GP
2
1
C280
SC10U6D3V3MX-GP
2
1
SC10U6D3V3MX-GP
2
1
C261
C271
C281
SCD22U6D3V2KX-1GP
1.5A
1
1
1
C284
SCD22U6D3V2KX-1GP
C274
1
C255
DY
2
DY
2
DY
2
ACPU1A
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
2
D1
D2
D3
D4
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
J3
J2
J5
K5
N1
P1
P3
P4
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
HT LINK
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
AE2
AE3
AE4
AE5
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
Y1
W1
Y4
Y3
R2
R3
T5
R5
HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7
HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
C
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7
HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15
HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
HT_NB_CPU_CLK_L1
HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
C
B
HT_CPU_NB_CLK_H0 8
HT_CPU_NB_CLK_L0 8
HT_CPU_NB_CLK_H1 8
HT_CPU_NB_CLK_L1 8
HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1
8
8
8
8
B
SKT-CPU638P,DANUB
62.10055.111
SKT-BGA638H176
A
JE70-DN
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU_HT_LINK I/F_(1/4)
Size
Document Number
Rev
A3
Date:
5
4
3
2
JE70-DN
Monday, March 01, 2010
Sheet
1
SB
4
of
63
5
4
3
2
1
ACPU1C
MEM:DATA
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA_DQS0_P
MEM_MA_DQS0_N
MEM_MA_DQS1_P
MEM_MA_DQS1_N
MEM_MA_DQS2_P
MEM_MA_DQS2_N
MEM_MA_DQS3_P
MEM_MA_DQS3_N
MEM_MA_DQS4_P
MEM_MA_DQS4_N
MEM_MA_DQS5_P
MEM_MA_DQS5_N
MEM_MA_DQS6_P
MEM_MA_DQS6_N
MEM_MA_DQS7_P
MEM_MA_DQS7_N
Place near to CPU
D
4.7u x 4
1
1
1
1
C341
SC4D7U6D3V3MX-2GP
SC4D7U6D3V3MX-2GP
C317
C332
C316
SC4D7U6D3V3MX-2GP
0.22u X 2
1
1
1
1
C305
SCD22U6D3V2KX-1GP
C314
C327
C320
SC180P50V2JN-1GP
180P x 6
1
1
1
C315
SC180P50V2JN-1GP
SC180P50V2JN-1GP
C311
C321
SC180P50V2JN-1GP
C313
SC180P50V2JN-1GP
DY
2
DY
2
DY
2
DY
2
DY
2
DY
2
1D05V_S0
1500 mA
ACPU1B
CLOSE TO CPU
1D5V_S3
MEMZP
MEMZN
M_A_RST#
AF10
AE10
H16
T19
V22
U21
V19
T20
U19
U20
V20
J22
J20
N19
N20
E16
F16
Y16
AA16
P19
P20
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
R20
R23
J21
R19
T22
T24
MEMZP
MEMZN
RSVD_M1
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MA_RAS_L
MA_CAS_L
MA_WE_L
SKT-CPU638P,DANUB
VTT_SENSE
MEMVREF
RSVD_M2
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CKE0
MB_CKE1
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_RAS_L
MB_CAS_L
MB_WE_L
Y10
W17
VTT_SENSE
1
TP49 TPAD14-GP
VREF_DDR_CLAW
2
C
1D5V_S3
R429
39D2R2F-L-GP
1
2
1
2
R432
39D2R2F-L-GP
17
M_A_RST#
D10
C10
B10
AD10
VTT1
VTT2
VTT3
VTT4
VDDR
MEM:CMD/CTRL/CLK
VTT5
VTT6
VTT7
VTT8
VTT9
W10
AC10
AB10
AA10
A10
C364
SCD1U10V2KX-4GP
SRN1KJ-7-GP
2
1
1
1
M_B_RST#
M_B_RST#
16
C359
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
C358
SCD1U10V2KX-4GP
RN13
3
4
17
17
17
17
17
17
17
17
MEM_MA0_ODT0
MEM_MA0_ODT1
MEM_MA1_ODT0
MEM_MA1_ODT1
MEM_MA0_CS#0
MEM_MA0_CS#1
MEM_MA1_CS#0
MEM_MA1_CS#1
B18
W26
W23
Y26
V26
W25
U22
J25
H26
P22
R22
A17
A18
AF18
AF17
R26
R25
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
R24
U26
J26
U25
U24
U23
MEM_MB0_ODT0 16
MEM_MB0_ODT1 16
MEM_MB0_CS#0 16
MEM_MB0_CS#1 16
MEM_MB_CKE0 16
MEM_MB_CKE1 16
MEM_MB_CLK5_P 16
MEM_MB_CLK5_N 16
1110 swap RN48
17 MEM_MA_CKE0
17 MEM_MA_CKE1
17 MEM_MA_CLK5_P
17 MEM_MA_CLK5_N
17 MEM_MA_CLK1_P
17 MEM_MA_CLK1_N
17 MEM_MA_CLK7_P
17 MEM_MA_CLK7_N
17 MEM_MA_CLK4_P
17 MEM_MA_CLK4_N
B
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
E12
C15
E19
F24
AC24
Y19
AB16
Y13
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
SKT-CPU638P,DANUB
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
A12
B16
A22
E25
AB26
AE22
AC16
AD12
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
MEM_MB_DATA0 16
MEM_MB_DATA1 16
MEM_MB_DATA2 16
MEM_MB_DATA3 16
MEM_MB_DATA4 16
MEM_MB_DATA5 16
MEM_MB_DATA6 16
MEM_MB_DATA7 16
MEM_MB_DATA8 16
MEM_MB_DATA9 16
MEM_MB_DATA10 16
MEM_MB_DATA11 16
MEM_MB_DATA12 16
MEM_MB_DATA13 16
MEM_MB_DATA14 16
MEM_MB_DATA15 16
MEM_MB_DATA16 16
MEM_MB_DATA17 16
MEM_MB_DATA18 16
MEM_MB_DATA19 16
MEM_MB_DATA20 16
MEM_MB_DATA21 16
MEM_MB_DATA22 16
MEM_MB_DATA23 16
MEM_MB_DATA24 16
MEM_MB_DATA25 16
MEM_MB_DATA26 16
MEM_MB_DATA27 16
MEM_MB_DATA28 16
MEM_MB_DATA29 16
MEM_MB_DATA30 16
MEM_MB_DATA31 16
MEM_MB_DATA32 16
MEM_MB_DATA33 16
MEM_MB_DATA34 16
MEM_MB_DATA35 16
MEM_MB_DATA36 16
MEM_MB_DATA37 16
MEM_MB_DATA38 16
MEM_MB_DATA39 16
MEM_MB_DATA40 16
MEM_MB_DATA41 16
MEM_MB_DATA42 16
MEM_MB_DATA43 16
MEM_MB_DATA44 16
MEM_MB_DATA45 16
MEM_MB_DATA46 16
MEM_MB_DATA47 16
MEM_MB_DATA48 16
MEM_MB_DATA49 16
MEM_MB_DATA50 16
MEM_MB_DATA51 16
MEM_MB_DATA52 16
MEM_MB_DATA53 16
MEM_MB_DATA54 16
MEM_MB_DATA55 16
MEM_MB_DATA56 16
MEM_MB_DATA57 16
MEM_MB_DATA58 16
MEM_MB_DATA59 16
MEM_MB_DATA60 16
MEM_MB_DATA61 16
MEM_MB_DATA62 16
MEM_MB_DATA63 16
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
D
2
2
2
2
2
2
1
1
2
MEM_MB_CLK4_P 16
MEM_MB_CLK4_N 16
MEM_MB_ADD0 16
MEM_MB_ADD1 16
MEM_MB_ADD2 16
MEM_MB_ADD3 16
MEM_MB_ADD4 16
MEM_MB_ADD5 16
MEM_MB_ADD6 16
MEM_MB_ADD7 16
MEM_MB_ADD8 16
MEM_MB_ADD9 16
MEM_MB_ADD10 16
MEM_MB_ADD11 16
MEM_MB_ADD12 16
MEM_MB_ADD13 16
MEM_MB_ADD14 16
MEM_MB_ADD15 16
MEM_MB_BANK0 16
MEM_MB_BANK1 16
MEM_MB_BANK2 16
MEM_MB_RAS# 16
MEM_MB_CAS# 16
MEM_MB_W E# 16
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
2
17 MEM_MA_BANK0
17 MEM_MA_BANK1
17 MEM_MA_BANK2
17 MEM_MA_RAS#
17 MEM_MA_CAS#
17 MEM_MA_W E#
SC4D7U6D3V3MX-2GP
SC4D7U6D3V3MX-2GP
SCD22U6D3V2KX-1GP
A
62.10055.111
SC180P50V2JN-1GP
SC180P50V2JN-1GP
C
B
MEM_MB_DQS0_P
MEM_MB_DQS0_N
MEM_MB_DQS1_P
MEM_MB_DQS1_N
MEM_MB_DQS2_P
MEM_MB_DQS2_N
MEM_MB_DQS3_P
MEM_MB_DQS3_N
MEM_MB_DQS4_P
MEM_MB_DQS4_N
MEM_MB_DQS5_P
MEM_MB_DQS5_N
MEM_MB_DQS6_P
MEM_MB_DQS6_N
MEM_MB_DQS7_P
MEM_MB_DQS7_N
JE70-DN
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU_DDR_(2/4)
Size
Document Number
Rev
A3
Date:
5
4
3
2
JE70-DN
Monday, March 01, 2010
Sheet
1
SB
5
of
63

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