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ispPAC 10
TM
In-System Programmable Analog Circuit
Features
• IN-SYSTEM PROGRAMMABLE (ISP™) ANALOG CIRCUIT
— Four Instrument Amplifier Gain/Attenuation Stages
— Signal Summation (Up to 4 Inputs)
— Precision Active Filtering (10kHz to 100kHz)
— No External Components Needed for Configuration
— Non-Volatile E
2
CMOS
®
Cells (10,000 Cycles)
— IEEE 1149.1 JTAG Serial Port Programming
• FOUR LINEAR ELEMENT BUILDING BLOCKS
— Programmable Gain Range (0dB to 80dB)
— Bandwidth of 550kHz (G=1), 330kHz (G=10)
— Low Distortion (THD < -74dB max @ 10kHz)
— Auto-Calibrated Input Offset Voltage
• TRUE DIFFERENTIAL I/O (
±
3V RANGE)
— High CMR (69dB) Instrument Amplifier Inputs
— 2.5V Common Mode Reference on Chip
— Four Rail-to-Rail Voltage Outputs
• 28-PIN PLASTIC DIP OR SOIC PACKAGE
— Single Supply 5V Operation
• APPLICATIONS INCLUDE INTEGRATED:
— Single +5V Supply Signal Conditioning
— Active Filters, Gain Stages, Summing Blocks
— Analog Front Ends, 12-Bit Data Acq. Systems
— Sensor Signal Conditioning
Functional Block Diagram
OUT2+
OUT2–
IN2+
IN2–
TDI
TRST
VS
TDO
TCK
1
2
3
4
5
6
7
8
9
IA
IA
IA
IA
OA
OA
28 OUT1+
27 OUT1–
26 IN1+
IA
IA
25 IN1–
24 TEST
23 TEST
Configuration Memory
Analog Routing Pool
Reference & Auto-Calibration
22 VREF
OUT
21 GND
20 CAL
IA
IA
19 CMV
IN
18 IN3–
17 IN3+
16 OUT3–
TMS 10
IN4– 11
IN4+ 12
OUT4– 13
OUT4+ 14
Description
The ispPAC10 is a member of the Lattice family of In-
System Programmable analog circuits, digitally configured
via nonvolatile E
2
CMOS technology.
Analog function modules, called PACblocks™, replace
traditional analog components such as op amps and
active filters, eliminating the need for most external
resistors and capacitors. With no requirement for exter-
nal configuration components, ispPAC10 expedites the
design process, simplifying prototype circuit implemen-
tation and change, while providing high performance and
integrated functionality.
Designers configure the ispPAC10 and verify its perfor-
mance using PAC-Designer™, an easy to use, Microsoft
Windows
®
compatible development tool. Device pro-
gramming is supported using PC parallel port I/O
operations. A library of configurations is included with basic
solutions and examples of advanced circuit techniques.
The ispPAC10 is configured through its IEEE Standard
1149.1 (JTAG) compliant serial port. The flexible In-
System Programming capability enables programming,
verification and reconfiguration if desired, directly on the
printed circuit board.
OA
OA
15 OUT3+
Typical Application Diagram
5V
Vin
5V
12-Bit
Differential
Input ADC
Ain+
Ain-
Ref+
Ref-
ispPAC10
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-888-477-7537; FAX (503) 268-8037; http://www.latticesemi.com
November 1999
pac10_02
1
Specifications
ispPAC10
DC Electrical Characteristics
T
A
= 25
°
C; V
S
= 5.0V; Signal path = V
IN
to V
OUT
of one PACblock (second input unused); 1V
≤
V
OUT
≤
4V; Gain = 1; No output load.
Feedback enabled; Feedback capacitor = minimum; Auto-Cal initiated immediately prior. (Unless otherwise specified).
SYMBOL
Analog Input
V
IN±
(1)
V
OS
(2)
∆V
OS
/∆T
R
IN
C
IN
I
B
e
N
Analog Output
V
OUT±
(3)
PARAMETER
Input Voltage Range
CONDITION
MIN.
1
TYP.
MAX. UNITS
4
V
µV
mV
µV/°C
Ω
pF
pA
nV/√Hz
4
V
mA
V
dB
%
%
ppm/°C
dB
dB
0.2
3.25
%
V
ppm/°C
µA
µA
µV
RMS
dB
cycles
0.8
V
S
±10
+40/-70
0.5
V
V
µA
µA
V
V
V
mA
mW
Differential Offset Voltage (Input Referred)
Differential Offset Voltage Drift
Input Resistance
Input Capacitance
Input Bias Current
Input Noise Voltage Density
Voltage Output Range
G = 10
G=1
-40 to +85°C
20
0.2
50
10
9
2
3
38
1
10
2.495
0
2.500
100
1.0
at DC
At 10kHz, Referred to Input, G = 10
R
L
= 300Ω Differential
Source/Sink
(V
OUT+
+ V
OUT-
)/2 ; V
IN+
= V
IN–
Each individual PACblock
R
L
= 300Ω Differential
Between Two Inputs of Same PACblock
-40 to +85°C
Differential at 1kHz
Single-ended at 1kHz
Nominally 2.500V
Optional External Common-Mode Voltage
-40 to +85°C
(VREF
OUT
=
±1%)
Source
(VREF
OUT
=
±1%)
Sink
10MHz Bandwidth; 1µF Bypass Capacitor
1kHz
10K
0
2.0
0V
≤
TCK Input
≤
V
S
0V
≤
CAL, TDI, TMS, TRST Inputs
≤
V
S
I
OL
= 4.0mA
I
OH
= -1.0mA
2.4
4.75
V
S
= 5.0V
V
S
= 5.0V
-0.2
1.25
I
OUT±
Output Current
V
CM
Common Mode Output Voltage
Static Performance
G
Programmable Gain Range
Gain Error
Gain Matching
Gain Drift
Power Supply Rejection
2.505
20
4.0
3.0
∆G/∆T
PSR
20
80
77
Common Mode Reference Output (VREF
OUT
)
VREF
OUT
Reference Output Voltage Range
CMV
IN
(4)
Common Mode Voltage Input
IREF
OUT
Reference Output Voltage Drift
Reference Output Current
Reference Output Noise Voltage
Reference Power Supply Rejection
Programming
Erase/Reprogram Cycles
Digital I/O
V
IL
V
IH
I
IL
, I
IH
V
OL
V
OH
Power Supplies
V
S
I
S
P
D
Temperature Range
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Low Voltage (TDO)
Output High Voltage (TDO)
Operating Supply Voltage
Supply Current
Power Dissipation
50
50
350
40
80
5.0
5.25
23
115
Operation
-40
+85
°C
Storage
-65
+150
°C
Notes: (1) A wider input range of 0.7V to 4.3V is typical, but not guaranteed. Inputs larger than this will be clipped. Input signals are also
subject to common-mode voltage limitations. Refer to the table of conditions in this datasheet. (2) To maintain specification offset voltage
performance, auto-calibration must be performed at least once every 24 hours. To insure full spec performance an additional auto-calibration
should also be performed after initial turn-on and the device reaches thermal stability. (3) Unloaded outputs can swing to within a few
millivolts of 0V and V
S
. (4) The user-provided voltage on this pin (CMV
IN
) becomes an optional (selected via programming) alternative to the
default 2.5V VREF
OUT
.
2
Specifications
ispPAC10
AC Electrical Characteristics
T
A
= 25
°
C; V
S
= 5.0V; Signal path = V
IN
to V
OUT
of one PACblock (2nd input unused); 1V
≤
V
OUT
≤
4V; Gain = 1; No output load
Feedback enabled; Feedback capacitor = minimum; Auto-Cal initiated immediately prior. (Unless otherwise specified).
SYMBOL
Dynamic Performance
THD
Total Harmonic Distortion
Differential
Single-Ended
Differential
F
IN
= 10kHz
F
IN
= 100kHz
0.1Hz to 100kHz
10kHz
100kHz
-88
-72
-67
-63
103
69
55
550
330
5.0
0.1%
6V
DIFF
Input Step
Between Any Two Channels
Number of Poles in Range > 120
Deviation From Calculated Value
10kHz to 100kHz
-40 to +85°C
10
1.0
0.02
330
7.5
4.0
-90
100
5.0
3.2
-74
-62
dB
dB
dB
dB
dB
dB
dB
kHz
kHz
kHz
V/µs
µs
dB
kHz
%
%
%/°C
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNITS
SNR
CMR
BW
BW
FP
SR
t
S
Single-Ended
Signal to Noise
G = 1 to 10
Common Mode Rejection (V
IN
= 1V to 4V)
Note: V
IN+
and V
IN-
connected together
Small Signal Bandwidth
G=1
G = 10
Full Power Bandwidth
Slew Rate
V
IN
= 6
V
DIFF
, V
OUT
= -3dB; G=1
Settling Time
Crosstalk
Filter Characteristics
F
0
∆F
0
∆F
0
/∆T
Filter Pole Programming Range
Absolute Pole Frequency Accuracy
Pole Step Size (Between Calculated Poles)
Pole Frequency Change vs. Temperature
Absolute Maximum Ratings
Supply Voltage V
S
....................................... -0.5 to +7V
Logic and Analog Input Voltage Applied ........... 0 to V
S
Logic and Analog Output Short Circuit Duration ..... Indefinite
Lead Temperature (Soldering, 10 sec.) .............. 260°C
Ambient Temperature with Power Applied ... -55 to 125°C
Storage Temperature ................................ -65 to 150°C
Note: Stresses above those listed may cause perma-
nent damage to the device. These are stress only
ratings and functional operation of the device at
these or at any other conditions above those
indicated in the operational sections of this speci-
fication is not implied.
Package Options
1
1
ispPAC10
28-Pin PDIP
Part Number Description
ispPAC 10 – XX X X
ispPAC10
28-Pin SOIC
ispPAC10 Ordering Information
Ordering Number
ispPAC10-01PI
ispPAC10-01SI
Package
28-Pin DIP
28-Pin SOIC
Device Family
Device Number
Performance Grade
01 = Standard
Package
P = PDIP, S = SOIC
Grade
Blank = Commercial
I = Industrial Temperature
3
Specifications
ispPAC10
Timing Specifications
T
A
= 25
°
C; V
S
= +5.0V (Unless otherwise specified).
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNITS
Dynamic Performance
tckmin
Minimum Clock Period
tckh
TCK High Time
tckl
TCK Low Time
tmss
tmsh
tdis
tdih
tdozx
tdov
tdoxz
trstmin
tpwp
tpwe
tpwcal1
tcalmin
tpwcal2
TMS Setup Time
TMS Hold Time
TDI Setup Time
TDI Hold Time
TDO Float to Valid Delay
TDO Valid Delay
TDO Valid to Float Delay
Minimum reset pulse width
Time for a programming operation
Time for an erase operation
Time for auto-cal operation on power-up
Minimum auto-cal pulse width
Time for user initiated auto-cal operation
200
50
50
15
10
15
10
60
60
60
Executed in Run-Test/Idle
Executed in Run-Test/Idle
Automatically executed at power-up
40
Executed on rising edge of CAL
100
40
80
80
100
100
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
ns
ms
tckh
TCK
tmss
tmsh
tckl
tckmin
tpwp, tpwe
TCK
tmss
(PRGUSR/UBE executed in
Run-Test/Idle state)
tmss
TMS
tdis
tdih
TMS
TDI
tdozx
tdov
tdoxz
CAL
tcalmin
(Note: CAL internally
initiated at device turn-on.)
VOUT = 0VDIFF
TDO
VOUT
tpwcal1, tpwcal2
4
Specifications
ispPAC10
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
OUT2+
OUT2-
IN2+
IN2-
TDI
TRST
VS
TDO
TCK
TMS
IN4-
IN4+
OUT4-
OUT4+
OUT3+
OUT3-
IN3+
IN3-
CMV
IN
Name
Output 2(+)
Output 2(-)
Input 2(+)
Input 2(-)
Test Data In
Test Reset
Supply Voltage
Test Data Out
Test Clock
Test Mode Select
Input 4(-)
Input 4(+)
Output 4(-)
Output 4(+)
Output 3(+)
Output 3(-)
Input 3(+)
Input 3(-)
Input for V
CM
Reference
Description
Differential output pin, V
OUT
+
. (Plus complement of V
OUT
with respect to VREF
OUT
,
where differential V
OUT
= V
OUT
+
- V
OUT
-
).
Differential output pin, V
OUT
-
. (Minus component, where differential V
OUT
= V
OUT
+
- V
OUT
-
).
Differential input pin, V
IN
+
. (Plus V
IN
, where differential V
IN
= V
IN
+
- V
IN
-
).
Differential input pin, V
IN
-
. (Minus component of differential V
IN
, where V
IN
= V
IN
+
- V
IN
-
).
Serial interface logic input pin. Input data valid on rising edge of TCK.
Serial interface logic reset pin (input). Asynchronously resets logic controller. Active low.
Reset is equivalent of power-on default.
Analog supply voltage pin (5V nominal).
Should be bypassed to GND with 1µF and .01µF capacitors.
Serial interface logic output pin. Input data valid on falling edge of TCK.
Serial interface logic clock pin (input). Best analog performance when TCK is idle.
Serial interface logic mode select pin (input).
Differential input pin, V
IN
-
Differential input pin, V
IN
+
Differential output pin, V
OUT
-
Differential output pin, V
OUT
+
Differential output pin, V
OUT
+
Differential output pin, V
OUT
-
Differential input pin, V
IN
+
Differential input pin, V
IN
-
Input pin for optional (external) analog Common-Mode Voltage (V
CM
). Replaces VREF
OUT
(+2.5V) for any so programmed PACblock as its common-mode output voltage value.
Digital input pin. Commands an auto-calibration sequence on a rising edge.
Ground pin. Should normally be connected to analog ground plane.
Common-mode voltage reference output pin (+2.5V nominal). Must be bypassed to GND
with a 0.1µF capacitor.
Manufacturing test pin. Connect to GND for proper circuit operation.
Manufacturing test pin. Connect to GND for proper circuit operation.
Differential input pin, V
IN
-
Differential input pin, V
IN
+
Differential output pin, V
OUT
-
Differential output pin, V
OUT
+
CAL
Auto-Calibrate
GND
Ground
VREF
OUT
Common-Mode Reference
TEST
TEST
IN1-
IN1+
OUT1-
OUT1+
Test Pin
Test Pin
Input 1(-)
Input 1(+)
Output 1(-)
Output 1(+)
Connection Notes
1. All inputs and outputs are labeled with plus (+) and
minus (-) signs. Polarity is labeled for reference and
can be selected externally by reversing pin connec-
tions or internally under user programmable control.
2. All analog output pins are “hard-wired” to internal
output devices and should be left open if not used.
Outputs of uncommitted PACblocks are forced to
VREF
OUT
(2.5V) and can be used as low impedance
reference output buffers. V
OUT+
and V
OUT-
should not
be tied together as unnecessary power will be dissi-
pated.
3. When the signal input is single-ended, the other half of
the unused differential input must be connected to a
DC common-mode reference (usually VREF
OUT
, 2.5V).
Pin Configuration
OUT2+
OUT2–
IN2+
IN2–
TDI
TRST
VS (5V)
TDO
TCK
TMS
IN4–
IN4+
OUT4–
OUT4+
1
OUT1+
OUT1–
IN1+
IN1–
TEST (tie to GND)
TEST (tie to GND)
VREFout
GND (0V)
CAL
CMVin
IN3–
IN3+
OUT3–
OUT3+
28-Pin
Top View
ispPAC10
5

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