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Using the ispPAC 20
for Advanced
Voltage Monitoring
TM
Introduction
The ispPAC20 is a member of the Lattice Semiconductor
family of In-System Programmable (ISP™) analog cir-
cuits. Analog building blocks in the ispPAC family replace
traditional analog components such as op amps and
active filters and eliminate the need for most external
resistors and capacitors. The device is programmed
while it is in-circuit, using Windows
®
-based PAC-De-
signer™ software. After simulation in PAC-Designer, the
design is downloaded to the part, which utilizes nonvola-
tile E
2
CMOS
®
technology to configure such things as
circuit topologies, gains, and feedback capacitor values.
Figure 1 is a block diagram of the ispPAC20. The device
includes two programmable gain blocks, called
PACblocks, with differential instrumentation-amplifier
inputs, differential outputs, and variable gains from
±
1 to
±
10 in integer steps. The feedback capacitors in these
blocks can be selected from a 128-value range of ap-
proximately 1 pF to 63 pF for active filter applications. The
feedback resistors of these devices can also be switched
in for gain or switched out so they act as integrators. One
Figure 1. ispPAC20 Block Diagram
OUT1
MSEL = A
of the PACblock inputs has a two-position multiplexer,
and another has a pin-controllable inverter, which can
also be controlled from certain internal nodes. In addition,
an 8-bit DAC and two comparators are included in the
ispPAC20. Comparator connections can be made di-
rectly inside the device, or an external, differential
comparator input may be applied. The comparison thresh-
old voltage can be set by the DAC, and the output of one
comparator can also be clocked in a register, or used with
the output of the second comparator in an exclusive-OR
gate or to drive an RS flip-flop for additional logic function-
ality. Reference voltages of 1.5V and 3.0V are available,
as is a standard 2.50V bandgap reference. All of these
features make the ispPAC20 a very versatile device for
solving analog circuitry problems.
In this application note, the ispPAC20 will be configured
to monitor power supply and other important voltages.
The combination of gain and DAC-controlled comparator
threshold voltages can give a large variety of monitoring
choices. It will be seen that the gain, DAC and compara-
tor sections make the ispPAC20 an ideal device for such
applications.
CPIN
1.07 pF
IN1
a
1
IA1
b
IN2
IA2
2.5V
1
IN3
1
IA3
3V
1.5V
DACOUT
2.5V
Code: 80h
0.0000V
E2Cells/Parallel inputs
PACblock 2
1.07 pF
CP2
CP2OUT
Digital outputs=enabled
-1
OA1
PACblock 1
CP1
Direct
CP1OUT
Hyst=on
WINDOW
XOR
3V
1.5V
OUT2
IA4
-1
SRE=on
OA2
Polarity Control: PC pin
PC = 0
UES Bits = 0000000
an6013_01
1
November 1999
Using the ispPAC20 for
Advanced Voltage Monitoring
Figure 2. Over-voltage Sensing
VIN
R
1
63.50 pF
IN2
10
IA3
C
1
R
2
2.49K
SRE=on
IA4
VREF
OUT
(pin 2)
-1
CP2
Polarity Control: PC pin
PC=0
Gain - see Table 1 for values.
R
1
- see Table 2 for values.
C
1
- see Table 2 for values.
DACOUT
Code: 80h
0.0000V
CP2OUT
OA2
-1
OUT2
Hyst=off
PACblock 2
CP1
Direct
or
Clocked
CP1OUT
WINDOW
XOR
Over-voltage Monitoring
A voltage signal is typically monitored by connecting it to
one of the ispPAC20’s input pins, and connecting the
output of the PACblock amplifier to a comparator input.
The comparator output can then be used to signal when
an over-voltage or under-voltage condition is occurring.
It can also be used with external logic to register that a
fault has occurred. Running the signal through a PACblock
will allow the addition of filtering, increasing the sensitiv-
ity for improved DAC response, or taking advantage of
the high-impedance instrumentation-amplifier inputs, if
desired. Or it could be run directly to one of the compara-
tor inputs. Note that when the ispPAC20 is acting as a
level monitor, the register at the output of CP1 should be
set for “Direct” mode rather than “Clocked” mode.
Differential input signals can be wired directly to the
ispPAC20’s inputs if they are properly centered at 2.50V
and within 1V to 4V in value. If they need to be centered
at 2.50V, coupling capacitors and decoupling resistors to
the internal reference can be used. If they are larger than
4V, attenuation resistors can be used. Single-ended
inputs can be monitored by making use of the ispPAC20’s
2.50V bandgap reference, which provides an excellent
comparison and offset voltage. To make use of it for this
purpose, simply wire it to the minus input pin of one of the
IC’s differential inputs, and connect either the signal to be
monitored or an attenuated version of it to the plus input
pin. See Figure 2, which shows an example of a +5V
power supply being monitored. The +5V signal must be
attenuated by resistors to be close to 2.50V for this
procedure to work properly. Changing the DAC output
will allow for some variation in determining the nominal
attenuated signal, but maximum performance is achieved
when it is set for 2.50V.
To examine the details of a typical power-supply monitor-
ing circuit using the ispPAC20, take a closer look at
Figure 2. In this example, if the power supply voltage is
nominally 5V
±
5%, then the expected voltage range is
4.75V to 5.25V. To set an over-voltage threshold of
5.25V, divide the 5V input to match the 2.50V reference
voltage of the ispPAC device. Connect it to the plus input
pin of IN2 and wire VREF
OUT
to the associated minus
input pin. As shown in the figure, a capacitor may be used
from the plus input to ground to reduce the effects of any
noise or spikes on the supply. Since we will be using the
IA3 - OA2 PACblock, set OA2’s feedback capacitor to its
maximum value to reduce the amplification of spikes or
high-frequency noise. Connect IN2 to IA3, and set the IA3
gain to ten, so that 250 mV of difference becomes 1.25V
(0.250V / 2 (to get from 5.0V to 2.50V) x 10 (PACblock
gain) = 1.25V). Note that amplifying the monitored input
signal prior to comparison increases the sensitivity of the
circuit. Connect the OA2 output to the (differential) plus
inputs of CP1, and draw the other comparator inputs to
the DAC output. The output range of the DAC is 6V (± 3V
differentially), resulting in an LSB of 23.4mV. Setting the
output of the DAC to 1.266V (B6h) will cause the output
of CP1 to go high when the supply exceeds 5.253V.
Table 1 shows the settings for other values of supply over
voltage for Figure 2.
Table 1. Supply Over-voltage Threshold vs. Gain
and DAC Output for 5V
V
IN
= 5V (R1 = R2 = 2.49K)
Desired Over-voltage
PACblock Gain
DAC Setting
V
IN
Trigger Threshold
0.250V 0.500V 1.000V
10
B6h
5
B6h
1
96h
5.253V 5.506V 6.032V
2
Using the ispPAC20 for
Advanced Voltage Monitoring
Figure 3. Under-voltage Sensing
VIN
R
1
63.50 pF
IN2
10
IA3
C
1
R
2
2.49K
SRE=on
IA4
VREF
OUT
(pin 2)
-1
CP2
Polarity Control: PC pin
PC=0
Gain - see Table 1 for values.
R
1
- see Table 2 for values.
C
1
- see Table 2 for values.
DACOUT
Code: 80h
0.0000V
CP2OUT
OA2
-1
OUT2
Hyst=off
WINDOW
XOR
PACblock 2
CP1
Direct
CP1OUT
As can be seen, the basic procedure for setting the
PACblock gain and threshold voltage is to make sure that
the PACblock output stays within its 1-to-4-volt linear
range, with the threshold set relatively near the center of
that range. More specifically, the voltage difference be-
tween the comparison threshold and 2.50V must still be
within the 1-to-4-volt window after amplification in IA3.
Table 2 shows the recommended resistor and capacitor
values to divide other power supply voltages to 2.50V,
allowing use of the internal bandgap voltage reference
for offset purposes at the inputs of the IAs.
Table 2. Resistor Values to Obtain 2.50V
CP1’s inverting inputs are connected to OA2’s outputs,
with the positive inputs of the comparator now being
connected to the DAC outputs. This way, if the input
voltage falls below the set threshold, the comparator
output will be high.
Another way to check for under-voltage is to simply
connect the OA2 output to the minus input of CP2, as
shown in Figure 4. The inversion-triangle on the plus
input of CP2 inverts the sense of the DAC-generated
differential threshold voltage, allowing CP2 to check for
voltages below nominal at the same time as CP1 checks
for voltages above nominal. The same 0.253V, 0.506V or
1.032V offsets that are generated for over-voltage sens-
ing will be subtracted from nominal values for
under-voltage sensing at CP2.
V
IN
R
1
V
OUT
2.49K
R
2
Over-voltage and Under-voltage Monitoring
For monitoring over-voltage and under-voltage applica-
tions on one signal source, CP1 and CP2 can be used
together. The WINDOW pin (an XOR of CP1OUT and
CP2OUT) will signify that the condition of both signals is
acceptable by outputting a 0. But if either an over-voltage
or an under-voltage fault is present, WINDOW will be-
come a 1, signifying that a voltage-error state exists.
Figure 4 also demonstrates this connection.
V
IN
R
1
Actual V
Requiv.
-3dB
if C
1
0.1µ
1.0µ
10.0µ
5V
2.49K
2.5V
1.25KΩ
1.27kHz
127Hz
12.7Hz
12V
9.53K
2.486V
1.974K
806Hz
80.6Hz
8.06Hz
15V
12.4K
2.508V
2.080K
765Hz
76.5Hz
7.65Hz
If R
2
= 2.49K
Dual-positive Voltage Monitoring
If only one pair of external connections is added, a single
ispPAC20 can be used to monitor two positive voltages
for either over-voltage or under-voltage conditions. See
Figure 5 for a typical connection. PACblock 1 is used to
add gain, buffering and/or filtering, if necessary, to the
second supply. To get OA1’s output to a comparator,
Under-voltage Monitoring
Figure 3 shows a typical connection to monitor for under-
voltages on a power supply or other voltage source.
3
Using the ispPAC20 for
Advanced Voltage Monitoring
Figure 4. Dual-voltage Sensing (Single Supply)
VIN
R
1
63.50 pF
IN2
10
IA3
C
1
R
2
2.49K
SRE=on
IA4
VREF
OUT
(pin 2)
-1
CP2
Polarity Control: PC pin
PC=0
Gain - see Table 1 for values.
R
1
- see Table 2 for values.
C
1
- see Table 2 for values.
DACOUT
Code: 80h
0.0000V
CP2OUT
OA2
-1
OUT2
Hyst=off
WINDOW
XOR
PACblock 2
CP1
Direct
CP1OUT
Figure 5. Dual-positive Voltage Sensing
VIN1
R
1
63.50 pF
IN2
1
IA3
C
1
R
2
2.49K
IA4
VREF
OUT
(pin 2)
-1
Polarity Control: PC pin
PC=0
Gain - see Table 1 for values.
R
1
, R
3
- see Table 2 for values.
C
1
, C
2
- see Table 2 for values.
MSEL=A
63.50 pF
a
VIN2
R
3
IN1
b
IA1
OUT1
1
IA2
C
2
R
4
2.49K
DACOUT
VREF
OUT
(pin 2)
Code: 80h
0.0000V
OA1
IN3
CP2
PACblock 1
-1
CP2OUT
OUT2
SRE=on
Hyst=off
OA2
XOR
WINDOW
PACblock 2
CP1
Direct
CP1OUT
4
Using the ispPAC20 for
Advanced Voltage Monitoring
external wiring must be run from OUT1 to either IN3
(whose pins are close to OUT1) or to CPIN. Note that the
connections between OUT1 and IN3 or CPIN are in-
verted in order for the inverted comparison at CP2 to be
correct. Because of the inverter on the plus input of CP2,
all comparisons made with it have the output go low if
either input exceeds the threshold. To change the com-
parison from over-voltage sense to under-voltage sense,
swap the polarity of the signal gain rather than these
comparator inputs.
diode in series to limit possible damage to the ispPAC20
if the voltages exceed expected values.
In the above circuit, the input voltage is divided to one-
tenth of its original value so that changes around the input
are also divided to one-tenth of their values. While this is
not as convenient as one-half of the original value (if the
part were run from -5V), if it is acceptable to use OA1 to
obtain a buffered VREF
OUT
, the ispPAC20 can be pow-
ered from +5V instead of -5V. An alternative scheme
would raise the values of the resistors by roughly 20,
allowing the 50
µA-limited
VREF
OUT
signal to be used
directly at the input rather than buffering it through OA1.
This should be done with caution, however, because the
high impedance presented at the input may negate the
effects of this mode of buffering if RF noise or ground-
loop noise is present.
If giving up OA1 to get a buffered VREF
OUT
is not
possible, the ispPAC20 can also be powered from -5V (to
the IC’s GND pins) and ground (to the IC’s VS pin) (see
Figure 7). The reference output voltage becomes -2.5V,
which is now somewhat variable since it is referenced to
-5V, which may be less stable than ground. The logic
levels from the comparator outputs are now -5V and 0V.
In order to level-shift these outputs to +5V so they can be
utilized by external logic, use a standard opto-isolator
such as the 4N26 or PC713V (or dual PC827). One must
Negative-voltage Monitoring
Monitoring negative voltages with the ispPAC20 is a little
more challenging because the device is designed to run
from a single positive supply. However, there are two
ways to monitor negative signals. The first method in-
volves tying one of the external voltage-divider resistors
(R2) to the buffered VREF
OUT
instead of ground (see
Figure 6). The negative input voltage is divided to
VREF
OUT
to give a positive voltage at the input to IA3. As
an example, if V
IN
is -5V, a voltage divider with better than
0.2% accuracy can be established to VREF
OUT
to give a
+1.755V input value using R1 = 20.0K and R2 = 2.21K.
The DAC output voltage can then be offset to this value
(60h gives 2.50 - .750 = 1.750V). Depending on what
value is expected for the negative input voltage, it might
be wise to include a 5V zener diode plus a hot-carrier
Figure 6. Over-voltage Sensing (Negative Supply)
-VIN
R
1
(20.0K)
IN2
∆
=
-0.745
1
IA3
SRE=on
IA4
VREF
OUT
(pin 2) 50µA max
-1
CP2
Polarity Control: PC pin
PC=0
DACOUT
Gain - see Table 1 for values.
R
1
- see Table 2 for values.
C
1
- see Table 2 for values.
63.50 pF
Code: 60h
-0.7500V
CP2OUT
OA2
-1
PACblock 2
CP1
OUT2
Hyst=off
WINDOW
XOR
Direct
63.50 pF
CP1OUT
1.755V.
C
1
R
2
2.21K
+2.50V.
OUT1
OA1
buffered
VREF
OUT
5

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