8C25KDataSheet.pdf

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Cypress MicroSystems
CY8C25xxx/26xxx Data Sheet
The CY8C25xxx/26xxx family of Programmable System-on-Chip (PSoC
) microcontrollers
replaces many MCU-based system components with
one
single-chip, programmable device. A
single PSoC microcontroller offers a fast core, Flash program memory, and SRAM data memory
with configurable analog and digital peripheral blocks in a range of convenient pin-outs and
memory sizes. The driving force behind this innovative programmable system-on-a-chip comes
from user configurability of analog and digital arrays, the PSoC
b
locks.
Powerful Harvard Architecture Processor with
Fast Multiply/Accumulate
Processor speeds to 24MHz
Register speed memory transfers
Instruction set that is easy to learn and use
Flexible addressing modes
Bit manipulation on I/O and memory
8x8 multiply, 32-bit accumulate
Programmable Pin Configurations
Schmitt trigger TTL I/O pins
Configurable output drive to 25 mA with
internal pull-up or pull-down resistors, open
drain, or active driver
Interrupt on Pin Change
Precision, Programmable Clocking
Internal 48/24MHz oscillator (+/- 2.5%, no
external components)
External 32.768kHz crystal oscillator (optional
precision source for PLL)
Internal Low Speed Oscillator for Watchdog
and Sleep
Dedicated Peripherals
Watchdog/Sleep Timers
5V and 3V Brownout protection with user-
configurable trip voltages
On-chip voltage reference
On-chip temperature sensor
Fully Static CMOS Devices utilizing advanced
FLASH technology
Low power at high speed
Operating voltage from 3.0 to 5.5 VDC
Operating voltages from 0.9V to 5.5 VDC using
on-chip switch mode voltage pump
o
o
Wide temperature range: -40 C to + 85 C
Complete Development Tools
Powerful integrated development environment
(PSoC Designer
)
Low-cost, in-circuit emulator and programmer
Flexible On-Chip Memory
FLASH memory, 4k to 16 kbytes, depending
on device
100,000 erase/write cycles
SRAM memory, 128 to 256 bytes, depending
on device
Serial programming capability
Partial Flash updates
Flexible protection model
EEPROM emulation in Flash
Programmable System-on-Chip (PSoC ) Blocks
On-chip, user configurable analog and digital
peripheral blocks
PSoC blocks can be used individually or in
combination
Analog PSoC blocks provide:
Up to 12 bit Delta-Sigma ADC
Up to 8 bit Successive Approximation ADC
Up to 12 bit Incremental ADC
Up to 8 bit direct DAC
Programmable gain
Sample and hold
Programmable filters
Differential comparators
On-chip temperature sensor
Digital PSoC blocks provide:
Multipurpose timers: event timing, real-time
clock, pulse width modulation (PWM) and
PWM with deadband
CRC modules
Full-duplex UARTs
SPI
master or slave configuration
Complex clocking sources for analog
PSoC blocks
Advance Information CMS10002A-R1.19
Copyright
2000-2001 Cypress MicroSystems, Inc.
1
Cypress MicroSystems
CY8C25xxx/26xxx Data Sheet
25122 PDIP
P0[3]
P0[1]
P1[1]/CrysIn/SCLK
V
ss
1
2
3
4
8
7
6
5
V
cc
P0[2]
P0[0]
P1[0]/CrysOut/SDATA
V
cc
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[7]
P0[1]
P0[3]
P0[5]
P0[7]
P4[1]
P1[7]
P1[5]
P1[3]
P1[1]/CrysIn/SCLK
P1[1]/CrysIn/SCLK
V
ss
P1[0]/CrysOut/SDATA
P0[7]
P0[5]
P0[3]
P0[1]
SMP
P2[7]
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1]/CrysIn/SCLK
V
ss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
cc
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[4]
P2[2]
P2[0]
X
res
P1[6]
P1[4]
P1[2]
P1[0]/CrysOut/SDATA
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[7]
P3[5]
P3[3]
P3[1]
SMP
P4[7]
P4[5]
P4[3]
P4[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]/CrysIn/SCLK
V
ss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
ss
P1[0]/CrysOut/SDATA
P1[2]
P1[4]
P1[6]
P4[0]
P0[7]
P0[5]
P0[3]
P0[1]
SMP
P1[7]
P1[5]
P1[3]
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
cc
P0[6]
P0[4]
P0[2]
P0[0]
X
res
P1[6]
P1[4]
P1[2]
P2[5]
P2[3]
P2[1]
P3[7]
P3[5]
P3[3]
P3[1]
SMP
P4[7]
P4[5]
P4[3]
1
44 43 42 41 40 39 38 37 36 35 34
2
3
4
5
6
7
8
9
10
11
26643 TQFP
12 13 14 15 16 17 18 19 20 21 22
33
32
31
30
29
28
27
26
25
24
23
P2[4]
P2[2]
P2[0]
P3[6]
P3[4]
P3[2]
P3[0]
X
res
P4[6]
P4[4]
P4[2]
Advance Information CMS10002A-R1.19
Copyright
2000-2001 Cypress MicroSystems, Inc.
26233 PDIP/SOIC/SSOP
26443
PDIP/SOIC/SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
cc
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[4]
P2[2]
P2[0]
P3[6]
P3[4]
P3[2]
P3[0]
X
res
P4[6]
P4[4]
P4[2]
P4[0]
P5[2]
P5[0]
P1[6]
P1[4]
P1[2]
P1[0]/CrysOut/SDATA
26643 PDIP/SSOP
2
Cypress MicroSystems
1
CY8C25xxx/26xxx Data Sheet
Functional Overview .......................................................................................................................................................... 5
1.1
1.2
1.3
Key Features ................................................................................................................................................................. 5
Pin-out Descriptions ..................................................................................................................................................... 6
Block Diagram ............................................................................................................................................................ 10
2
Family Architecture ......................................................................................................................................................... 11
2.1
2.2
2.3
2.4
Introduction................................................................................................................................................................. 11
Registers...................................................................................................................................................................... 12
Addressing Modes ....................................................................................................................................................... 14
Instruction Set Summary ............................................................................................................................................. 18
3
Memory Organization...................................................................................................................................................... 19
3.1
3.2
Flash Program Memory Organization........................................................................................................................ 19
RAM Data Memory Organization ............................................................................................................................... 19
4
Register Organization ...................................................................................................................................................... 20
4.1
4.2
4.3
Introduction................................................................................................................................................................. 20
Register Bank 0 Map................................................................................................................................................... 21
Register Bank 1 Map................................................................................................................................................... 22
5
I/O Ports............................................................................................................................................................................ 23
5.1
5.2
Introduction................................................................................................................................................................. 23
I/O Registers ............................................................................................................................................................... 25
6
Clocking ............................................................................................................................................................................ 28
6.1
6.2
Oscillator Options....................................................................................................................................................... 28
System Clocking Signals.............................................................................................................................................. 30
7
Interrupts .......................................................................................................................................................................... 34
7.1
7.2
7.3
7.4
Overview ..................................................................................................................................................................... 34
Interrupt Vectors ......................................................................................................................................................... 35
Interrupt Masks ........................................................................................................................................................... 35
Interrupt on Pin Change ............................................................................................................................................. 36
8
PSoC Blocks ...................................................................................................................................................................... 37
8.1
8.2
8.3
Overview ..................................................................................................................................................................... 37
Digital PSoC Blocks.................................................................................................................................................... 37
Global Inputs and Outputs .......................................................................................................................................... 45
3
Advance Information CMS10002A-R1.19
Copyright
2000-2001 Cypress MicroSystems, Inc.
Cypress MicroSystems
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
9
CY8C25xxx/26xxx Data Sheet
Potential Digital User Modules .................................................................................................................................. 46
Analog PSoC Blocks ................................................................................................................................................... 53
Analog Comparator Bus ............................................................................................................................................. 74
Analog Synchronization .............................................................................................................................................. 74
Analog I/O................................................................................................................................................................... 76
Analog Reference and Bias Control............................................................................................................................ 78
Analog Modulator.................................................................................................................................................... 79
Potential Analog User Modules............................................................................................................................... 80
Temperature Sensing Capability ............................................................................................................................. 80
Special Features of the CPU ............................................................................................................................................ 81
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
Multiplier / Accumulator............................................................................................................................................. 81
Decimator.................................................................................................................................................................... 84
Reset ............................................................................................................................................................................ 85
Sleep States ................................................................................................................................................................. 87
Supply Voltage Monitor .............................................................................................................................................. 88
Internal Voltage Reference.......................................................................................................................................... 89
Switch Mode Pump...................................................................................................................................................... 90
Supervisor ROM / System Supervisor Call Instruction ............................................................................................... 91
Flash Program Memory Protection ............................................................................................................................ 92
Programming Requirements, Flow Chart, and Step Descriptions .......................................................................... 92
Programming Wave Forms...................................................................................................................................... 95
Programming File Format ...................................................................................................................................... 95
10 Development Tools ........................................................................................................................................................... 96
10.1
Overview
................................................................................................................................................................... 96
10.2
10.3
Integrated Development Environment Subsystems .................................................................................................. 97
Hardware Tools....................................................................................................................................................... 97
11 DC and AC Characteristics ............................................................................................................................................. 98
11.1
11.2
11.3
Absolute Maximum Ratings ..................................................................................................................................... 98
DC Characteristics .................................................................................................................................................. 98
AC Characteristics ................................................................................................................................................ 101
12 Packaging Information .................................................................................................................................................. 103
13 Ordering Guide .............................................................................................................................................................. 110
Advance Information CMS10002A-R1.19
Copyright
2000-2001 Cypress MicroSystems, Inc.
4
Cypress MicroSystems
1
Functional Overview
CY8C25xxx/26xxx Data Sheet
The CPU heart of the 8C25K family is a high performance, 8-bit, next generation M8C Harvard architecture microprocessor.
Separate program and memory busses allow for faster overall throughput. Processor clock speeds to 24MHz are available.
The processor may also be run at lower clock speeds for power-sensitive applications. A rich instruction set allows for efficient
high-level language support as well as bit-manipulation capabilities.
All devices in this family include both Analog and Digital Configurable System Modules (PSoC blocks). These blocks enable
the user to define unique functions during configuration of the device. Included are twelve analog PSoC blocks and eight
digital PSoC blocks. Potential applications for the digital PSoC blocks are timers, counters, UARTs, CRC generators, PWMs,
and other functions. The analog PSoC blocks can be used for SAR ADCs, Multi-slope ADCs, programmable gain,
programmable filter, DACs, and other functions. Higher order user modules such as modems, complex motor control, and
complete sensor signal chains can be created from these building blocks. This allows for an unprecedented level of flexibility
and integration in microcontroller-based systems.
A Multiplier/Accumulator (MAC) is available on all devices in this family. The MAC is implemented on this device as a
peripheral that is mapped into the register space. When the input registers are written to the MAC, the result of an 8x8 multiply
and a 32-bit accumulate are available to be read from the output registers on the next instruction cycle.
The number of general purpose I/Os available in this family of parts range from 6 to 44. Each of these I/O pins has a variety of
programmable options. In the output mode, the user can select the drive strength desired. Any pin can serve as an interrupt
source, and can be selected to trigger on positive edges, negative edges, or any change. Digital signal sources can be routed
directly from a pin to the digital PSoC blocks. Some pins have additional capability to route analog signals to the Analog PSoC
blocks.
Multiple oscillator options are available for use in clocking the CPU, Analog PSoC blocks and Digital PSoC blocks. These
options include an internal main oscillator running at 48/24MHz, an external crystal oscillator for use with a 32.768kHz watch
crystal, and an internal low-speed oscillator for use in clocking the PSoC blocks and the Watchdog/Sleep timer. User
selectable clock divisors allow for optimizing code execution speed and power tradeoffs
Several different device types in this family will provide various amounts of code and data memory. The code space ranges in
size from 4K to 16K bytes of user programmable Flash memory. This memory is programmed serially in either a programming
station or on the user board. The endurance on the Flash memory is 100,000 erase/write cycles. The data space ranges in
size from 128 to 256 bytes of user SRAM.
A powerful and flexible protection model secures the user’s sensitive information. This model allows the user to selectively
lock blocks of memory for read and write protection. This allows partial code updates without exposing proprietary information.
Devices in this family range from 8 pins through 48 pins in PDIP, SOIC and SSOP packages.
1.1
Key Features
8C25122A
8C26233A
3.0 - 5.5v
8
256
8
12
16
Yes
20 PDIP
20 SOIC
20 SSOP
8C26443A
3.0 - 5.5v
16
256
8
12
24
Yes
28 PDIP
28 SOIC
28 SSOP
8C26643A
93.7kHz - 24MHz
3.0 - 5.5v
16
256
8
12
40/44
Yes
48 PDIP
48 SSOP
44 TQFP
Operating Frequency
Operating Voltage
Program Memory (KBytes)
Data Memory (Bytes)
Digital PSoC Blocks
Analog PSoC Blocks
I/O Pins
External Switch Mode Pump
Available Packages
93.7kHz - 24MHz
3.0 - 5.5v
4
128
8
12
6
No
8 PDIP
93.7kHz - 24MHz 93.7kHz - 24MHz
Advance Information CMS10002A-R1.19
Copyright
2000-2001 Cypress MicroSystems, Inc.
5

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