//////////////////////////////////////// // $Author: alanwang $ // $Date: 2010/11/18 $ // $Id: //depot/BCM2091/BCM2091Init/init_bcm2091b0_crkt.txt#102 $ //////////////////////////////////////// // For B0 we should do hpclkgen_sel_txmmd_pol = 1 to select txmmd_p clock thru hpclkgen. hptx to hptx_ds end to end gate level timing simulations has violations with default value (of "0") // hpclkgen_sel_txmmd_pol = 1; RF_WRITE INITONLY 0x0001 0x1000 //hpseq_ldoPowerMode = 1, Sleep. CAUTION: This is the same as the POR value. But for DVT lab testing, it is convenient to force the ldoMode to 1 RF_WRITE INITONLY 0x0221 0x100f //digital DCOC coefficients for 2G Rx RF_WRITE INITONLY 0x0222 0xfada //digital DCOC coefficients for 2G Rx RF_WRITE INITONLY 0x0223 0xfada //digital DCOC coefficients for 2G Rx RF_WRITE INITONLY 0x0224 0x2799 //enable 2G and 3G Rx data path gain scaling and bit shift compensation RF_WRITE INITONLY 0x022e 0x0f3c //3G RX group delay equalizer coeff[5] RF_WRITE INITONLY 0x022f 0xc4ba //3G RX group delay equalizer coeff[4] RF_WRITE INITONLY 0x0240 0xcdeb //3G RX group delay equalizer coeff[3] RF_WRITE INITONLY 0x0241 0x10b1 //3G RX group delay equalizer coeff[2] RF_WRITE INITONLY 0x0242 0xed7b //3G RX group delay equalizer coeff[1] RF_WRITE INITONLY 0x0243 0x183c //3G RX group delay equalizer coeff[0] RF_WRITE INITONLY 0x0364 0x01ce //IQLOFT/Filter Cal: hprx_envSel=1 RF_WRITE INITONLY 0x0366 0x0190 //set ACI dectection freq0 to 400kHz for LO swap RF_WRITE INITONLY 0x0367 0x0190 //set ACI dectection freq1 to 400kHz for LO swap RF_WRITE INITONLY 0x0368 0x0190 //set ACI dectection freq2 to 400kHz for LO swap RF_WRITE INITONLY 0x0369 0x0190 //set ACI dectection freq3 to 400kHz for LO swap RF_WRITE INITONLY 0x0376 0x6400 //set ACI dectection threshold power to 25dB for LO swap RF_WRITE INITONLY 0x0377 0x0041 //for DVT cricket board, by default we are using 8-bit data capture. For platform, this depends on the baseband. Bit[3]=0 to enable digital DCOC for 3G RX. RF_WRITE INITONLY 0x0379 0x0080 //swap IQ for 3G RX RF_WRITE INITONLY 0x037a 0x000f //wprx_dsp_dcoc_coeff_1[17:16] fast and slow mode DCOC coefficients RF_WRITE INITONLY 0x037c 0xfef9 //wprx_dsp_dcoc_coeff_1[15:0] fast mode DCOC coefficients (BW=0.7KHz) RF_WRITE INITONLY 0x037d 0xfef9 //wprx_dsp_dcoc_coeff_1[15:0] slow mode DCOC coefficients (BW=0.7KHz) RF_WRITE INITONLY 0x037e 0x0022 //enable LO swap RF_WRITE INITONLY 0x0410 0x02a3 //TEMPORARY (DVT only, waiting for FPGA Update) use A0 POR value RF_WRITE INITONLY 0x0411 0x01ee //TEMPORARY (DVT only, waiting for FPGA Update) use A0 POR value RF_WRITE INITONLY 0x0425 0x0005 //enable freq_dev_frac bypass, hptx_freq_dev_frac_adjust set to 1.0 for now RF_WRITE INITONLY 0x0426 0xCDB8 // proemphasis_rdata_0, Yiannis RF_WRITE INITONLY 0x0427 0x00BA // proemphasis_rdata_1, Yiannis RF_WRITE INITONLY 0x042a 0x8A8D // proemphasis_rdata_4, Yiannis RF_WRITE INITONLY 0x042b 0xC3E9 // proemphasis_rdata_5, Yiannis RF_WRITE INITONLY 0x042c 0x3648 // proemphasis_rdata_6, Yiannis RF_WRITE INITONLY 0x0438 0x0001 //hptx_lut_rd_mode = 1, to access LUT at HS-DPCCH boundary in 3g mode #if defined(_RHEA2091_) RF_WRITE INITONLY 0x0444 0x5000 //hptx_ramp_td_mid_slot = 0xa #else RF_WRITE INITONLY 0x0444 0x8028 //hptx_ramp_td_mid_slot = 0x10 #endif // _RHEA2091_ RF_WRITE INITONLY 0x045a 0x014a //set hptx_gain_bkoff for ROTW based on system document release v20 RF_WRITE INITONLY 0x0446 0x6000 //hptx_ramp_tramp_mid_slot = 0xc #if defined(_RHEA2091_) RF_WRITE INITONLY 0x044c 0x24b4 //hptx_pac_sh_delay_dn = 45 #else RF_WRITE INITONLY 0x044c 0x24f8 //hptx_pac_sh_delay_dn = 0x3e #endif // _RHEA2091_ RF_WRITE INITONLY 0x045e 0x0013 //hptx_dgs_dsc_byp = 1 (use digital gain from dynamic write instead of product of dgs and dsc),hptx_dgs_dsc_ovr=1(to load bkoff?)hptx_dig_gain_ovr=1(so hptx_dig_gain_ovrVal is not used) RF_WRITE INITONLY 0x0472 0x6200 //hptx_master_timer_en = 1 RF_WRITE INITONLY 0x04a5 0x0aa8 //bit 1 selects the unit for hptx_clpc_timer0/1; set it to 0 for Cx4 step. If it's 1 then Cx2 step. RF_WRITE INITONLY 0x04ae 0x002d //hptx_prePA_TC0 = 5, hptx_prePA_TC1 = 5 (2 MSBs driven by LUT; this mainly sets the LSB) #if defined(_RHEA2091_) RF_WRITE INITONLY 0x04c2 0x3c91 //hptx_clpc_en = 1,hptx_feedbackenable=1,hptx_clpc_bypass=1 #else RF_WRITE INITONLY 0x04c2 0x3c90 //hptx_clpc_en = 1,hptx_feedbackenable=1,hptx_clpc_bypass=1 #endif // _RHEA2091_ RF_WRITE INITONLY 0x04c5 0x15a0 //3G CLPC:hptx_clpc_fine_gain=0x32, hptx_clpc_gain_medium=2, hptx_clpc_gain_fast=2,hptx_clpc_gain_slow=3 RF_WRITE INITONLY 0x04c6 0x0018 //3G CLPC:hptx_clpc_fast_length=24 RF_WRITE INITONLY 0x04c7 0x0800 //3G CLPC:hptx_clpc_gain_mode=1 RF_WRITE INITONLY 0x04cb 0xe79c //3G CLPC:hptx_gain_correction_scale=3 RF_WRITE INITONLY 0x04d2 0x620c //3G CLPC:hptx_loop_filter_init_ctrl=1,hptx_loop_filter_numerator=12,hptx_loop_filter_gain_indicator_slow=3 RF_WRITE INITONLY 0x04d6 0x0200 //3G CLPC:hptx_clpc_tx_pwr_thresh_high = 2 dBm RF_WRITE INITONLY 0x04d7 0xfe00 //3G CLPC:hptx_clpc_tx_pwr_thresh_low = -2 dBm RF_WRITE INITONLY 0x04da 0x1800 //3G CLPC:hptx_loop_filter_gain_indicator_medium=3 RF_WRITE INITONLY 0x04db 0x0400 //3G CLPC:hptx_loop_filter_fb_gain_storage=0 RF_WRITE INITONLY 0x04f0 0x5109 //2G CLPC:hptx_pc_RegulatorStartTime= 14 + hptx_ramp_tdped_first_slot*3+ceil(hptx_2g_psk_delay_sel/2)=81,hptx_pc_RegulatorStopDelta=2+ceil(hptx_2g_psk_delay_sel/2) RF_WRITE INITONLY 0x04f1 0x00e2 //2G CLPC:hptx_pc_StepSettlingTime=0,hptx_pc_MinFeedbackPwr=-30 RF_WRITE INITONLY 0x04f2 0x0601 //2G CLPC:hptx_pc_IntegralFactor=0.045,hptx_pc_ProportionalFacto=0.01. RF_WRITE INITONLY 0x04f3 0x807f //2G CLPC:hptx_pc_RegulatorLowerLimit=128,hptx_pc_RegulatorUpperLimit=127 RF_WRITE INITONLY 0x04f4 0x0000 //2G CLPC:hptx_pc_RegulatorHysteresis{1|2] = 0 RF_WRITE INITONLY 0x04fa 0x7e2c //2G CLPC: hptx_pc_ReadbackWindow=3,hptx_pc_Hysteresis[1|2]_ovr=1,hptx_pc_BiasCodeIgnore=1,hptx_pc_EnableRegulator=1,hptx_pc_PwrCtrlTdlSel=12,hptx_pc_VdetFiltBW=1 RF_WRITE INITONLY 0x04fd 0x00e5 //hptx_3gsync_mode = 7, hptx_en_sync_cntr=5 RF_WRITE INITONLY 0x0503 0x0002 //3G CLPC:hptx_clpc_gain_rback_en=1 RF_WRITE INITONLY 0x0509 0x0C99 //hptx_lut_rd_addr_base3 = 25, hptx_lut_rd_addr_base2 = 25 //RF_WRITE INITONLY 0x050a 0x2532 //hptx_lut_rd_addr_base5 = 74, hptx_lut_rd_addr_base4 = 50 //RF_WRITE INITONLY 0x050b 0x254A //hptx_lut_rd_addr_base7 = 74, hptx_lut_rd_addr_base6 = 74 RF_WRITE INITONLY 0x0511 0x4010 //2G CLPC:hptx_2gclpc_resolution_ctrl=16 RF_WRITE INITONLY 0x0515 0x8000 //hptx_prePA_lut_ctrl = 1 RF_WRITE INITONLY 0x0516 0x0130 //3G CLPC:hptx_prePA_quant_sel=9, hptx_prePA_loop_gain=16 RF_WRITE INITONLY 0x0517 0x000e //3G CLPC:hptx_prePA_engage_time=14 RF_WRITE INITONLY 0x0518 0x003f //3G CLPC:hptx_prePA_gain_thresh_low = 0, hptx_prePA_gain_thresh_high=63 RF_WRITE INITONLY 0x051c 0x0932 //2G CLPC:hptx_pc_RegulatorStartTime1=50 (this equals to 13+hptx_ramp_td_mid_slot*3+ceil(hptx_2g_psk_delay_sel/2),hptx_pc_RegulatorStopDelta1=2+ceil(hptx_2g_psk_delay_sel/2) RF_WRITE INITONLY 0x0600 0xd5ff //hpseq_bandTx_V = LB2,hpseq_bandTx_II = HB2 #if defined(_RHEA2091_) RF_WRITE INITONLY 0x0602 0x08e4 //hpseq_bandRx_V = LB2,hpseq_bandRx_III = HB2,hpseq_bandRx_II = HB1 #else #if defined(UMTS_BAND_2_4_5) RF_WRITE INITONLY 0x0602 0x08d4 //hpseq_bandRx_V = LB2,hpseq_bandRx_III = HB2,hpseq_bandRx_II = HB1 #else RF_WRITE INITONLY 0x0602 0x18d4 //hpseq_bandRx_V = LB2,hpseq_bandRx_III = HB2,hpseq_bandRx_II = HB1 #endif #endif // _RHEA2091_ RF_WRITE INITONLY 0x0603 0x08c1 //hpseq_bandRx_X = HB3,hpseq_bandRx_IX = HB2, hpseq_bandRx_VIII = LB1, hpseq_bandRx_VI = LB2 RF_WRITE INITONLY 0x0604 0x030A //hpseq_bandTx_X = HB2,hpseq_tx_GSM850 = LB1, hpseq_tx_GSM900 = LB1 #if defined(_RHEA2091_) #ifndef AUTO_BAND #if defined(UMTS_BAND_1_8) RF_WRITE INITONLY 0x0605 0x021A //hpseq_rx_GSM850 = LB2, hpseq_rx_GSM900 = LB1, hpseq_rx_DCS = HB2, hpseq_rx_PCS = HB1 #else RF_WRITE INITONLY 0x0605 0x0053 //NA-BOM #endif #endif #else //NOT RHEA2091 #if defined(UMTS_BAND_2_4_5) RF_WRITE INITONLY 0x0605 0x005A //hpseq_rx_GSM850 = LB2, hpseq_rx_GSM900 = LB1, hpseq_rx_DCS = HB2, hpseq_rx_PCS = HB1 #else RF_WRITE INITONLY 0x0605 0x021A //hpseq_rx_GSM850 = LB2, hpseq_rx_GSM900 = LB1, hpseq_rx_DCS = HB2, hpseq_rx_PCS = HB1 #endif #endif RF_WRITE INITONLY 0x0631 0x0009 //Rx IQ Calibration reset starting coefficient RF_WRITE INITONLY 0x063a 0x1001 //enable digital DCOC for 2G Rx #if defined(_RHEA2091_) RF_WRITE INITONLY 0x064e 0x80ff //3G CLPC:hpseq_clpc_en=1 #else RF_WRITE INITONLY 0x064e 0x00ff //3G ...
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