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9/11/16
CS 422/522 Design & Implementation
of Operating Systems
Lecture 3: Project Overview
Zhong Shao
Dept. of Computer Science
Yale University
Acknowledgement:
some slides are taken from previous versions of the CS422/522 lectures taught by Prof. Bryan Ford
and Dr. David Wolinsky, and also from the official set of slides accompanying the OSPP textbook by Anderson and Dahlin.
Debugging as engineering
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Much of your time in this course will be spent
debugging
–  In industry, 50% of software dev is debugging
–  Even more for kernel development
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How do you reduce time spent debugging?
–  Produce working code with smallest effort
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Optimize a process involving you, code, computer
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Debugging as science
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Understanding -> design -> code
–  not the opposite
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Form a hypothesis that explains the bug
–  Which tests work, which don’t. Why?
–  Add tests to narrow possible outcomes
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Use best practices
–  Always walk through your code line by line
–  Module tests – narrow scope of where problem is
–  Develop code in stages, with dummy replacements for later
functionality
x86 abstract model
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I/O: Communicating data to and from devices
CPU: Logic for performing computation
Memory: Storage
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x86 CPU/memory interaction
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Memory stores instruction and data
CPU interprets instructions
x86 implementation
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EIP points to next instruction
Incremented after each instruction
x86 instructions are not fixed length
EIP modified by CALL, RET, JMP, and conditional JMP
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x86 general purpose registers (GPR)
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Temporary registers
Contents may be changed by instructions
Contents not changed by interrupts / exceptions / traps
EDI/ESI used by string ops but also as GPR
x86 memory models
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Real mode
with segmentation (16-bit mode)
–  Used by early OSes
–  All x86 still boots in Real Mode for “compatibility” reasons
–  You can only use 1MB memory (4-bit segment + 16-bit address)
PhysicalAddress = segment * 16 + offset
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Protected mode
w. segmentation & paging (32-bit)
–  4GB memory
–  Segmentation done via GDT (Global Descriptor Table)
*  A code segment descriptor holding a base address
*  A data segment descriptor holding a base address
*  A TSS segment descritor …
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x86 segmentation registers
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8086 registers 16-bit w/20-bit bus addresses
Solution: segment registers
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CS: code segment, EIP
SS: stack segment, ESP and EBP
DS: data segment, register mem ops
ES: string segment, string ops
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Linear address computation:
–  EIP => CS:EIP = 0x8000:0x1000 = 0x81000
–  ESP => SS:ESP = 0xF800:0x1000 = 0xF9000
–  (EAX) => DS:EAX = 0xC123:0x1000 = 0xC2230
x86 real mode
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8086 16-bit with
20-bit address bus
Stored in segment
registers CS, DS,
ES, FS
Logical address:
segment:offset
Physical address:
segment*0x10 +
offset
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