LA-8951P Vius3 Vius4 Rev 1.0.pdf

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Compal Confidential
1
Model Name : VIUS3/S4
File Name : LA-8951PR01
BOM P/N:43
1
Compal Confidential
2
2
VIUS3/S4 M/B Schematics Document
Intel Ivy Bridge ULV Processor + Panther Point PCH
AMD Seymour XT
3
2011-12-28
REV:0.1
3
4
4
Security Classification
Issued Date
2011/06/24
Compal Secret Data
Deciphered Date
2012/07/12
Title
Compal Electronics, Inc.
Cover Page
Sherry and Royal
Thursday, February 02, 2012
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.1
Sheet
1
of
55
Date:
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Compal confidential
File Name :VIUS3/VIUS4
Chief River
PCI-E X16
Gen 2
UP TO 1G
1
AMD Seymour XT
23mm *23mm
VRAM 128MB*16
gDDR3*4
Intel
IVY Bridge SV/ULV
(Sandy Bridge)
Processor
BGA1023
DDR3-SO-DIMM X1
BANK 0, 1
Dual Channel
DDR3-1066/1333(1.5V) for Sandy Bridge
DDR3-1600(1.5V) for Ivy Bridge
1
SATA3.0 HDD CONN
Std HDMI
Connector
2
HDMI 1.4a
FDI *8
100MHz
2.7GT/s
DMI2 *4
100MHz
5GT/s
6*SATA
(port0,1 Support SATA3)
SATA3.0 HDD (SSD)
LVDS
Connector
PX 5.0
Intel
Panther Point
6*PCI-E x1
2
4*USB3.0
14*USB2.0
PCI Express (Half)
Mini card Slot 1
WLAN/WiMAX
USB(WiMAX)
PCI-E(WLAN)
USB PORT 3.0 x1 (Left)
HM77/HM70
FCBGA 989 Balls
25mm*25mm
HD Audio
USB PORT 2.0 x2 (Right)
IO Board
PCI Express (Full)
Mini card Slot 2
SSD
mSATA(SSD)
Card Reader RTS 5178 (2in1)
IO Board
Gen 2
SPI ROM
BIOS
3
LPC BUS
4MB*1
2MB*1
EC
ENE KB9012
CMOS Camera
BlueTooth CONN
WLAN/WiMAX
WWAN
2Channel Speaker
3
WLAN/WiMAX
LAN(10/100/Giga)
Realtek
8105E-VD (10/100)
8111F-VL (Giga)
Int.KBD
Touch Pad
Audio Codec
RealTek
ALC259-VC2
Single Digital MIC
Audio Combo Jack
(APPLE type)
HeadPhone Output
Microphone Input
IO Board
4
RJ45 CONN
Sub-borad
4
Thermal Sensor
EMC1403
POWER BOARD
LED BOARD
Security Classification
Compal Secret Data
2011/07/21
Deciphered Date
2012/12/31
Title
Compal Electronics, Inc.
MB Block Diagram
Rev
0.2
Sheet
E
IO Board
A
B
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Thursday, February 02, 2012
2
of
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Voltage Rails
+5VS
power
plane
1
STATE
Full ON
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
HIGH
HIGH
HIGH
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LOW
+VALW
ON
ON
ON
ON
ON
+V
ON
ON
ON
OFF
OFF
+VS
ON
ON
OFF
OFF
OFF
Clock
ON
LOW
OFF
OFF
OFF
1
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
+3VS
+1.5VS
+1.05VS_VTT
+5VALW
+B
+3VALW
+1.5V_IO
+1.5V
+CPU_CORE
+VGA_CORE
+VCC_GFXCORE_AXG
+1.8VS
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
Board ID / SKU ID Table for AD channel
Vcc
Ra/Rc/Re
Board ID
State
+0.75VS
S0
O
O
O
O
O
O
O
O
O
O
S3
2
X
X
X
X
Address
1001_101xb
0
1
2
3
4
5
6
7
3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
V
AD_BID
min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
V
AD_BID
typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
V
AD_BID
max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
Porject
G-series
G-series
G-series
G-series
Y-series
Y-series
Y-series
Y-series
Phase
MP
PVT
DVT
EVT
EVT
DVT
PVT
MP
2
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
Address
X
X
X
Device
USB Port Table
USB 3.0
xHCI1
xHCI2
xHCI3
xHCI4
USB 2.0
UHCI0
UHCI1
EHCI1
UHCI2
UHCI3
Port
0
1
2
3
4
5
6
7
8
9
10
11
12
13
3 External
USB Port
USB 3.0 Port (Left Side)
Mini Card(WLAN)
X (USB PORT disabled on HM70 )
X (USB PORT disabled on HM70 )
X (USB PORT disabled on HM70 )
X (USB PORT disabled on HM70 )
USB/B (Right Side USB-BD)
USB/B (Right Side USB-BD)
USB Port (Right Side CR-BD)
BOM Structure Table
BTO Item
BOM Structure
INTEL UMA only
UMA@
GPU:Seymour XT
PX@ PX5@
HDMI
HDMI@
HDD1 (HM77 SATA 3.0)
HDD1@
HDD2 (HM70 SATA 2.0)
HDD2@
Interna-Intel-USB3.0
IU3@
Interna-Intel-USB2.0
IU2@
Blue Tooth
BT@
10/100 LAN
8105E@
GIGA LAN
8111F@
Connector
ME@
45 LEVEL
45@
Unpop
@
3
X
X
X
EC SM Bus1 address
Device
Smart Battery
0001 011X b
EC SM Bus2 address
Thermal Sensor F75303M
PCH SM Bus address
Device
DDR DIMM0
3
UHCI4
EHCI2
UHCI5
UHCI6
Address
1001 000Xb
1001 010Xb
DDR DIMM2
Camera (LVDS)
X (USB PORT disabled on HM70 )
X (USB PORT disabled on HM70 )
AMD-GPU SM Bus address
Device
Internal thermal sensor
HM70 Disable xHCI3,xHCI4
Address
1001 111Xb (0x9E)
SATA Port Table
SATA
SATA
SATA
SATA
SATA
SATA
HM77
HM70
P0
GEN3/2/1 GEN3/2/1
P1
GEN3/2/1
Disable
GEN2/1
P2
GEN2/1
Disable
P3
GEN2/1
GEN2/1
P4
GEN2/1
GEN2/1
P5
GEN2/1
PCIe Port Table
HM77
SSD
HDD (HM77)
HDD (HM70)
HM70
Enable
Enable
Enable
Enable
Disable
Disable
Disable
Disable
4
4
A
B
X
X
X
SV3+
V
X
HCP
Security Classification
Issued Date
C
rosneS
lamrehT
SV3+
V
X
X
X
X
NAWW MMIDOS 2109BK
NALW
X
X
SV3+
V
X
X
X
X
SV3+
V
X
X
SV3+
V
X
X
X
X
WLAV3+
TTAB
X
X
X
X
V
SV3+
V
X
X
X
X
AGV
elbaT lortnoC SUBMS
WLAV3+
WLAV3+
WLAV3+
ECRUOS
WLAV3+
WLAV3+
2109BK
2109BK
HCP
HCP
HCP
HM70 Disable P1,P3
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
P1
P2
P3
P4
P5
P6
P7
P8
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
LAN
WLAN
ATAD1LMS
KLC1LMS
ATAD0LMS
KLC0LMS
ATADBMS
KLCBMS
2AD_CE_BMS
2KC_CE_BMS
1AD_CE_BMS
1KC_CE_BMS
HM70 Disable P5,P6,P7,P8
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
Title
Compal Electronics, Inc.
Notes List
Document Number
Rev
0.2
Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
LA-7981P
Friday, February 03, 2012
3
of
55
Date:
5
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2
1
Power-Up/Down Sequence
1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up
sequence, though a shorter ramp-up duration is preferred.
D
Without BACO option :
PXS_RST# : Low -> Reset dGPU ; High ->Normal operation
PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON
BACO option :
PXS_RST# : High ->Normal operation (dGPU is not reset on BACO mode)
PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
dGPU Power Pins
PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT,
DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
DPLL_PVDD, MPV18, and SPV18
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and
SPV10
Voltage
1.8V
PX 3.0
OFF
BACO Mode Max current
ON
1679mA
D
2. VDDR3 should ramp-up before or simultaneously with VDDC.
3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and
VDD_CT have ramped up.
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
ramp-up (or vice versa).)
1.0V
1.0V
3.3V
Same as
VDDC
OFF
OFF
OFF
OFF
ON
ON
ON
ON
Same as
PCIE_VDDC
575mA
2A
190mA
70mA
VDDR3(3.3VGS)
PCIE_VDDC(1.0V)
VDDR1(1.5VGS)
C
Note: Do not drive any IOs before VDDR3 is ramped up.
PCIE_VDDC
VDDR3 , and A2VDD
BIF_VDDC (current consumption = 55mA@1.0V, in
BACO mode)
BIF_VDDC=VGA_CORE When GPU enable
BIF_VDDC=1.0V
When BACO
VDDR1
VDDC/VDDCI
1.5V
1.12V
OFF
OFF
OFF
OFF
2.8A
12.9A
C
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
iGPU
PERSTb
REFCLK
Straps Reset
Straps Valid
Global ASIC Reset
PXS_RST#
dGPU
PE_EN
BACO Switch
BIF_VDDC
PXS_PWREN
PX_mode
+3.3VALW
MOS
+3.3VGS
1
+1.0VGS
+1.5V
SI4800
+1.0V
+1.5VGS
Regulator
2
+1.8VGS
+B
Regulator
3
+VGA_CORE
B
B
+1.8V
T4+16clock
SI4800
5
4
PWRGOOD
CPU part
UCPU1
CPU1@
UCPU1
CPU2@
UCPU1
CPU3@
UCPU1
CPU4@
PCB part
ZZZ2
ZZZ5
ZZZ1
ZZZ3
ZZZ4
SA00005L510
I3_3217 1.8G
SA00005L900
I5_3427 1.8G
SA00004VZ00
I5_2557 1.4G
SA00005BJ40
977_1.4G
PCB 0R LA-8951P REV0 M/B
DA60000TO00
S512@
X7641338L01
Hynix
H512@
X7641338L02
Hynix
S1G@
X7641338L03
Hynix
H1G@
X7641338L04
Hynix
A
A
Security Classification
Issued Date
2011/06/15
Compal Secret Data
Deciphered Date
2012/07/11
Title
Compal Electronics, Inc.
VGA Notes List
LA-7981P
Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.2
4
of
55
Date:
Thursday, February 02, 2012
5
4
3
2
A
B
C
D
E
+1.05VS_VTT
R249
24.9_0402_1%
1
[15]
[15]
[15]
[15]
[15]
[15]
[15]
[15]
[15]
[15]
[15]
[15]
[15]
[15]
[15]
[15]
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
M2
P6
P1
P10
N3
P7
P3
P11
K1
M8
N4
R2
K3
M7
P4
T3
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
G3
G1
G4
H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6
G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4
PEG_COMP
2
UCPU1A
W=12mil L=500mil S=15mil
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
max length = 500 mils
- typical impedance = 14.5 mohms
1
1
PEG_GTX_C_HRX_N0
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_P15
PEG_HTX_GRX_N0
PEG_HTX_GRX_N1
PEG_HTX_GRX_N2
PEG_HTX_GRX_N3
PEG_HTX_GRX_N4
PEG_HTX_GRX_N5
PEG_HTX_GRX_N6
PEG_HTX_GRX_N7
PEG_HTX_GRX_N8
PEG_HTX_GRX_N9
PEG_HTX_GRX_N10
PEG_HTX_GRX_N11
PEG_HTX_GRX_N12
PEG_HTX_GRX_N13
PEG_HTX_GRX_N14
PEG_HTX_GRX_N15
PEG_HTX_GRX_P0
PEG_HTX_GRX_P1
PEG_HTX_GRX_P2
PEG_HTX_GRX_P3
PEG_HTX_GRX_P4
PEG_HTX_GRX_P5
PEG_HTX_GRX_P6
PEG_HTX_GRX_P7
PEG_HTX_GRX_P8
PEG_HTX_GRX_P9
PEG_HTX_GRX_P10
PEG_HTX_GRX_P11
PEG_HTX_GRX_P12
PEG_HTX_GRX_P13
PEG_HTX_GRX_P14
PEG_HTX_GRX_P15
C259
C276
C257
C274
C254
C272
C252
C270
C250
C268
C248
C267
C246
C264
C244
C262
C258
C277
C256
C275
C255
C273
C253
C271
C251
C269
C249
C266
C247
C265
C245
C263
C562
C582
C564
C584
C566
C587
C568
C589
C570
C591
C572
C593
C574
C594
C576
C597
C561
C583
C563
C585
C565
C586
C567
C588
C569
C590
C571
C592
C573
C595
C575
C596
Layout placement: Place close to U8 (GPU)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
PEG_GTX_HRX_N0
PEG_GTX_HRX_N1
PEG_GTX_HRX_N2
PEG_GTX_HRX_N3
PEG_GTX_HRX_N4
PEG_GTX_HRX_N5
PEG_GTX_HRX_N6
PEG_GTX_HRX_N7
PEG_GTX_HRX_N8
PEG_GTX_HRX_N9
PEG_GTX_HRX_N10
PEG_GTX_HRX_N11
PEG_GTX_HRX_N12
PEG_GTX_HRX_N13
PEG_GTX_HRX_N14
PEG_GTX_HRX_N15
PEG_GTX_HRX_P0
PEG_GTX_HRX_P1
PEG_GTX_HRX_P2
PEG_GTX_HRX_P3
PEG_GTX_HRX_P4
PEG_GTX_HRX_P5
PEG_GTX_HRX_P6
PEG_GTX_HRX_P7
PEG_GTX_HRX_P8
PEG_GTX_HRX_P9
PEG_GTX_HRX_P10
PEG_GTX_HRX_P11
PEG_GTX_HRX_P12
PEG_GTX_HRX_P13
PEG_GTX_HRX_P14
PEG_GTX_HRX_P15
PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P15
PEG_GTX_HRX_N[0..15]
PEG_GTX_HRX_P[0..15]
[22]
[22]
[22]
[22]
DMI
DMI
PEG_HTX_C_GRX_N[0..15]
PEG_HTX_C_GRX_P[0..15]
2
[15]
[15]
[15]
[15]
[15]
[15]
[15]
[15]
+1.05VS_VTT
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
U6
W10
W3
AA7
W7
T4
AA3
AC8
AA11
AC12
U11
AA10
AG8
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
eDP_COMPIO and ICOMPO signals
should be shorted near balls and
routed with typical impedance
<25 mohms
can't be left floating
,even if disable eDP function...
[15]
[15]
[15]
R247
24.9_0402_1%
[15]
[15]
W=12mil L=500mil S=15mil
EDP_COMP
3
AF3
AD2
AG11
AG4
AF4
AC3
AC4
AE11
AE7
AC1
AA4
AE10
AE6
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
eDP_AUX#
eDP_AUX
PCI EXPRESS -- GRAPHICS
[15]
[15]
[15]
[15]
[15]
[15]
[15]
[15]
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
U7
W11
W1
AA6
W6
V4
Y2
AC9
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
2
Intel(R) FDI
Intel(R) FDI
2
1
3
eDP
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
IVY-BRIDGE_BGA1023
@
Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
4
4
Security Classification
Issued Date
2011/06/24
Compal Secret Data
Deciphered Date
2012/07/12
Title
Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG
Sherry and Royal
Thursday, February 02, 2012
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Size
Document Number
Custom
Date:
Rev
0.1
Sheet
5
of
55

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