B570 Z570 V570 Wistron LZ57.91.4PA01.001.10290.pdf

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5
4
3
2
1
D
D
Lenovo IdeaPad B570 Z570 V570
Sandy Bridge
C
Intel PCH Cougar Point
2011-01-19
REV : XXX
C
B
DY :None Installed
UMA:UMA platform installed
PARK:DIS PARK platform installed
MADISON:DIS MADISON platform installed
Colay :Manual modify BOM
MUX : PX
BOM
B
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Siz e
A3
D ate:
5
4
3
2
D oc um ent N um b er
Tuesday, March 29, 2011
R ev
LZ57
S heet
1
-1
1
of
102
5
4
3
2
1
##OnMainBoard
USB BD
POWER BD
48.4IH03.0SA
D
Block Diagram
(UMA/Optimus co-lay)
4
88,89,90,91
SYSTEM DC/DC
48
RT8208B
INPUTS
OUTPUTS
DCBATOUT
0D85V_S0
CPU DC/DC
42~44
NCP6131
INPUTS
OUTPUTS
DCBATOUT
VCC_CORE
SYSTEM DC/DC
UP6111CQHC
45
INPUTS
OUTPUTS
DCBATOUT
1D05V_VTT
D
VRAM
1GB/512MB
DDR3
800MHz
Finger Printer BD
48.4IH04.0SA
IO BD
48.4IH02.0SA
Intel CPU
Sandy Bridge
PCIe x 16
(Discrete only)
Project code : 91.4PA01.001
PCB P/N
: 10290
Revision
: -SC
DDRIII 1066/1333/1666 Channel A
SYSTEM DC/DC
41
UP6183AQAG
INPUTS
OUTPUTS
DCBATOUT
5V_AUX_S5
3D3V_AUX_S5
5V_S5
3D3V_S5
AV BD
NVIDIA
N12P-GE/GV
83.84,85,86,87
DDRIII
Slot 0
1066/1333/1666
14
DDRIII
Slot 1
1066/1333/1666
15
SYSTEM DC/DC
DDRIII: 1066/1333/1666 MHz
4,5,6,7,8,9,10
DDRIII 1066/1333/1666 Channel B
46
UP6111C
INPUTS
OUTPUTS
1D5V_S3
DCBATOUT
DDR_VREF_S3
SYSTEM DC/DC
HDMI
C
51
FDI x 4 x 2
(UMA only)
HDMI
DMI x 4
44
NCP5911
INPUTS
OUTPUTS
DCBATOUT
VCC_GFXCORE
C
LCD
49
LVDS
RGB CRT
BD
PCIE x 1
GLAN
RTL8111E
31
CRT
Intel
RJ45
CONN
59
VGA
92
RT8208B
INPUTS
OUTPUTS
DCBATOUT
VGA_CORE
50
USB x 2
Bluetooth
CAMERA
63
USB2.0 x 5
PCH
Cougar Point
14 USB 2.0/1.1 ports
ETHERNET (10/100/1000Mb)
High Definition Audio
49
SATA ports (6)
PCIE ports (8)
LPC I/F
ACPI 1.1
PCIE x 1/USB2.0 x 1
Mini-Card
WLAN
65
TI CHARGER
40
BQ24745
OUTPUTS
INPUTS
PCIE x 1/USB2.0 x 1
Mini-Card
WWAN
66
SIM
66
26
+DC_IN_S5
+PBATT
DCBATOUT
PCIE x 1
35
NEC
uPD720200
MB
LDO
USB 3.0 x 1
62
47
RT9025
INPUTS
OUTPUTS
3D3V_S5
1D8V_S0
B
B
Finger Print
64
CardReader
Realtek
RTS5139
USB 2.0 x 1
USB 2.0 x 1/SATA x 1
SD/MMC+/MS/
MS Pro/xD
74
E-SATA/USB
57
comb
HDD
56
SYSTEM DC/DC
G9091-180T11U
24,93
INPUTS
OUTPUTS
26
3D3V_S5
3D3V_S0
1D5V_S5
1D8V_VGA_S0
17,18,19,20,21,22,23,24,25
AZALIA
SPI
SATA x 2
LPC Bus
ODD
56
LDO
46
RT9026
INPUTS
OUTPUTS
5V_S5
0D75V_S0
Internal DMIC
I/O BD
HP1
MIC IN
Azalia
CODEC
Realtek
RTC8111E
G1454
Flash ROM
4MB
60
29
LPC debug port
71
PCB LAYER
L1:Top
L2:GND
L3:Signal
L4:Signal
BOM
A
KBC
NUVOTON
NPCE795
2CH SPEAKER
SMBus
27
L5:VCC
L6:Signal
L7:GND
L8:Signal
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
G-Sensor
79
5
4
Touch
PAD
69
Int.
KB
69
3
Thermal
EMC2103-2-AP
25
28
Fan
28
2
Block Diagram
Size
A3
Date:
Document Number
Tuesday, March 29, 2011
Rev
LZ57
Sheet
1
-1
2
of
102
A
PCH Strapping
Name
SPKR
Huron River Schematic Checklist Rev.0_7
Schematics Notes
B
C
Processor Strapping
Pin Name
Strap Description
CFG[2]
PCI-Express Static
Lane Reversal
1:
0:
Huron River Schematic Checklist Rev.0_7
Default
Value
D
E
INIT3_3V#
Reboot option at power-up
Default Mode:
Internal weak Pull-down.
No Reboot Mode with TCO Disabled:
Connect to Vcc3_3 with
8.2-k
- 10-k weak pull-up resistor.
Weak internal pull-up. Leave as "No Connect".
GNT[3:0]# functionality is not available on Mobile.
Mobile: Used as GPIO only
Pull-up resistors are not required on these signals.
If pull-ups are used, they should be tied to the Vcc3_3power rail.
Enable Danbury:
Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.
Configuration (Default value for each bit is
1 unless specified otherwise)
Normal Operation.
Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
1
4
GNT2#/GPIO53
GNT1#/GPIO51
SPI_MOSI
GNT3#/GPIO55
CFG[4]
Disabled - No Physical Display Port attached to
1:
Embedded DisplayPort.
Enabled - An external Display Port device is
0:
connectd to the EMBEDDED display Port
PCI-Express
Port Bifurcation
Straps
11 : x16 - Device 1 functions 1 and 2 disabled
10 : x8, x8 - Device 1 function 1 enabled ;
function 2 disabled
01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
enabled
0
4
CFG[6:5]
Left floating, no pull-down required.
Disable Danbury:
11
NV_ALE
Enable Danbury:
Connect to +NVRAM_VCCQ with 8.2-kohm
weak pull-up resistor [CRB has it pulled up
with 1-kohm no-stuff resistor]
Leave floating (internal pull-down)
Disable Danbury:
CFG[7]
PEG DEFER TRAINING
1:
PEG Train immediately following xxRESETB de assertion
1
0:
PEG Wait for BIOS for training
NC_CLE
DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features.
High (1) - Security measure defined in the Flash Descriptor will be enabled.
Platform design should provide appropriate pull-up or pull-down depending on
the desired settings. If a jumper option is used to tie this signal to GND as
required by the functional strap, the signal should be pulled low through a weak
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently.
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for
strapping functions.
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no
confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher
suite with confidentiality
Note : This is an un-muxed signal.
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low.
Sampled at rising edge of RSMRST#.
CRB has a 1-kohm pull-up on this signal to +3.3VA rail.
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
5V_USBX_S3
1D5V_S3
DDR_VREF_S3
5V
1.5V
0.75V
S3
Voltage Rails
POWER PLANE
5V_S0
3D3V_S0
1D8V_S0
1D5V_S0
1D05V_VTT
0D85V_S0
0D75V_S0
VCC_CORE
VCC_GFXCORE
1D8V_VGA_S0
3D3V_VGA_S0
1V_VGA_S0
VOLTAGE
ACTIVE IN
5V
3.3V
1.8V
1.5V
1.05V
0.95 - 0.85V
0.75V
0.35V to 1.5V
0.4 to 1.25V
1.8V
3.3V
1V
DESCRIPTION
3
HAD_DOCK_EN#
/GPIO[33]
3
S0
CPU Core Rail
Graphics Core Rail
HDA_SDO
HDA_SYNC
GPIO15
BT+
DCBATOUT
5V_S5
5V_AUX_S5
3D3V_S5
3D3V_AUX_S5
3D3V_LAN_S5
6V-14.1V
6V-14.1V
5V
5V
3.3V
3.3V
3.3V
AC Brick Mode only
All S states
GPIO8
WOL_EN
Legacy WOL
2
GPIO27
3D3V_AUX_KBC
3.3V
DSW, Sx
ON for supporting Deep Sleep states
2
3D3V_AUX_S5
3.3V
G3, Sx
Powered by Li Coin Cell in G3
and +V3ALW in Sx
USB Table
Pair
Device
Touch Panel / 3G SIM
USB Ext. port 1 (HS)
Fingerprint
BLUETOOTH
Mini Card2 (WWAN)
CARD READER
X
X
USB Ext. port 4 / E-SATA /USB CHARGER
EC SMBus 2
PCH
eDP
SML1_CLK/SML1_DATA
SML1_CLK/SML1_DATA
SML1_CLK/SML1_DATA
PCIE Routing
LANE1
LANE2
LANE3
LANE4
LANE6
LANE7
LANE8
Mini Card2(WWAN)
Onboard LAN
Card Reader
Mini Card1(WLAN)
USB3.0
Intel GBE LAN
Dock
New Card
Pair
0
1
2
3
4
5
HDD1
HDD2
N/A
N/A
ODD
ESATA
0
1
2
3
SMBus ADDRESSES
I
2
C / SMBus Addresses
Device
Ref Des
HURON RIVER ORB
Address
Hex
Bus
SATA Table
SATA
Device
4
5
6
7
8
9
10
11
12
13
EC SMBus 1
Battery
CHARGER
BAT_SCL/BAT_SDA
BAT_SCL/BAT_SDA
BAT_SCL/BAT_SDA
1
LANE5
BOM
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
USB Ext. port 2
USB Ext. port 3
Mini Card1 (WLAN)
CAMERA
New Card
PCH SMBus
SO-DIMMA (SPD)
SO-DIMMB (SPD)
Digital Pot
G-Sensor
MINI
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
Title
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
Size
A3
Date:
Table of Content
Document Number
Tuesday, March 29, 2011
Rev
LZ57
Sheet
3
of
-1
102
5
SSID = CPU
4
3
2
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
1D05V_VTT
1
CPU1A
19 DMI_TXN[3:0]
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
1 OF 9
D
Note:
Intel DMI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap.
B27
B25
A25
B24
B28
B26
A24
B23
G21
E22
F21
D21
G22
D22
F20
C21
SANDY
DMI_RX#0
DMI_RX#1
DMI_RX#2
DMI_RX#3
DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3
DMI_TX#0
DMI_TX#1
DMI_TX#2
DMI_TX#3
DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_IRCOMP_R
R401
1
2
24D9R2F-L-GP
PEG_RXN[0..15]
PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0
PEG_RXP[0..15]
PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0
PEG_C_TXN15
PEG_C_TXN14
PEG_C_TXN13
PEG_C_TXN12
PEG_C_TXN11
PEG_C_TXN10
PEG_C_TXN9
PEG_C_TXN8
PEG_C_TXN7
PEG_C_TXN6
PEG_C_TXN5
PEG_C_TXN4
PEG_C_TXN3
PEG_C_TXN2
PEG_C_TXN1
PEG_C_TXN0
PEG_C_TXP15
PEG_C_TXP14
PEG_C_TXP13
PEG_C_TXP12
PEG_C_TXP11
PEG_C_TXP10
PEG_C_TXP9
PEG_C_TXP8
PEG_C_TXP7
PEG_C_TXP6
PEG_C_TXP5
PEG_C_TXP4
PEG_C_TXP3
PEG_C_TXP2
PEG_C_TXP1
PEG_C_TXP0
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
2
OPS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PEG_RXN[0..15]
83
D
19 DMI_TXP[3:0]
19 DMI_RXN[3:0]
19 DMI_RXP[3:0]
DMI
PCI EXPRESS* - GRAPHICS
PEG_RXP[0..15]
83
19 FDI_TXN[7:0]
C
Intel(R) FDI
Note:
Intel FDI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap.
19 FDI_TXP[7:0]
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
A21
H19
E19
F18
B21
C20
D18
E17
A22
G19
E20
G18
B20
C19
D19
F17
J18
J17
H20
J19
H17
FDI0_TX#0
FDI0_TX#1
FDI0_TX#2
FDI0_TX#3
FDI1_TX#0
FDI1_TX#1
FDI1_TX#2
FDI1_TX#3
FDI0_TX0
FDI0_TX1
FDI0_TX2
FDI0_TX3
FDI1_TX0
FDI1_TX1
FDI1_TX2
FDI1_TX3
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
NOTE.
If PEG is not implemented, the RX&TX pairs can be left as No Connect
PEG Static Lane Reversal
C401
C402
C403
C404
C405
C406
C407
C408
C409
C410
C411
C412
C413
C414
C415
C416
C417
C418
C419
C420
C421
C422
C423
C424
C425
C426
C427
C428
C429
C430
C431
C432
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0
PEG_TXP[0..15]
PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0
PEG_TXP[0..15]
83
PEG_TXN[0..15]
PEG_TXN[0..15]
83
C
Note:
Lane reversal does not apply to
FDI sideband signals.
19 FDI_FSYNC0
19 FDI_FSYNC1
19 FDI_INT
19 FDI_LSYNC0
19 FDI_LSYNC1
1D05V_VTT
R402
1
R403
1
2
24D9R2F-L-GP
2
Do Not Stuff
DP_COMP
eDP_HPD
A18
A17
B16
C15
D15
EDP_COMPIO
EDP_ICOMPO
EDP_HPD
EDP_AUX
EDP_AUX#
EDP_TX0
EDP_TX1
EDP_TX2
EDP_TX3
EDP_TX#0
EDP_TX#1
EDP_TX#2
EDP_TX#3
DY
Signal Routing Guideline:
EDP_ICOMPO keep W/S=12/15 mils and routing
length less than 500 mils.
EDP_COMPIO keep W/S=4/15 mils and routing
length less than 500 mils.
C17
F16
C16
G15
C18
E16
D16
F15
NOTE.
Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.
62.10055.321
delete R404&RN 401 @20100630
BOM
A
Title
eDP
B
B
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A
CPU (PCIE/DMI/FDI)
Size
A3
Date:
Document Number
Tuesday, March 29, 2011
Rev
LZ57
Sheet
4
of
-1
102
5
SSID = CPU
1D05V_VTT
R501
1
1
2
H_PROCHOT#
C502
SC47P50V2JN-3GP
Do Not Stuff
TP502
1
H_CATERR#
62R2J-GP
2
18
H_SNB_IVB#
1
SKTOCC#_R
4
CPU1B
3
2 OF 9
2
BCLK
BCLK#
A28
A27
CLK_EXP_P
CLK_EXP_N
20
20
SANDY
C26
AN34
SNB_IVB#
SKTOCC#
CLOCKS
MISC
Disabling Guidelines:
If motherboard only supports external graphics:
Connect DPLL_REF_SSCLK on Processor to GND through
1K +/- 5% resistor.
Connect DPLL_REF_SSCLK# on Processor to VCCP
through 1K +/- 5% resistorpower (~15 mW) may be
wasted.
CLK_DP_N_R
CLK_DP_P_R
RN502
1
2
4
3
Do Not Stuff
1D05V_VTT
1
Do Not Stuff
TP501
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
A16
A15
CLK_DP_P_R
CLK_DP_N_R
CLK_DP_P_R 20
CLK_DP_N_R 20
D
AL33
DY
R502
1
SM_DRAMRST#
R8
2
4K99R2F-L-GP
CATERR#
D
22,27
H_PECI
R513
AN33
THERMAL
PECI
SM_DRAMRST# 37
27,42 H_PROCHOT#
1
2
H_PROCHOT#_R
DDR3
MISC
AL32
PROCHOT#
56R2J-4-GP
Connect EC to PROCHOT# through inverting OD buffer.
22,36 H_THERMTRIP#
AN32
THERMTRIP#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
AK1
A5
A4
SM_RCOMP_0
R506
1
SM_RCOMP_1
R507
1
SM_RCOMP_2
R508
1
2
140R2F-GP
2
25D5R2F-GP
2
200R2F-L-GP
20100722 SA confirm.
Signal Routing Guideline:
SM_RCOMP keep routing length less than 500 mils.
AP29
AP27
AR26
AR27
AP30
AR28
AP26
XDP_PRDY#
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
1D05V_VTT
R503
1
H_CPUPWRGD_R
2
10KR2J-3-GP
PRDY#
PREQ#
PWR MANAGEMENT
19 H_PM_SYNC
AM34
PM_SYNC
JTAG & BPM
TCK
TMS
TRST#
TDI
TDO
11,22,36,97
H_CPUPWRGD
1
R504
2
H_CPUPWRGD_R
Do Not Stuff
AP33
UNCOREPWRGOOD
C
19,37 PM_DRAM_PWRGD
37 VDDPWRGOOD
1
R505
2
VDDPWRGOOD
Do Not Stuff
V8
DBR#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
XDP_DBRESET#
XDP_BPM0
XDP_BPM1
XDP_BPM2
XDP_BPM3
XDP_BPM4
XDP_BPM5
XDP_BPM6
XDP_BPM7
XDP_TMS
XDP_TDI
XDP_TDO
XDP_TCLK
1
2
3
4
RN501
8
7
6
5
C
DY
SM_DRAMPWROK
BUF_CPU_RST#
AR33
RESET#
SRN51J-1-GP
XDP_TRST#
R511
1
2
51R2J-2-GP
3D3V_S0
XDP_PREQ#
XDP_PRDY#
20100722 follow Astro add buffer
XDP_PREQ# 11
XDP_PRDY# 11
XDP_BPM0
XDP_BPM1
XDP_BPM2
XDP_BPM3
XDP_BPM4
XDP_BPM5
XDP_BPM6
XDP_BPM7
11
11
11
11
11
11
11
11
XDP_DBRESET#
1
R516
2
1KR2J-1-GP
B
DY
U501
1
2
3
NC#1
A
GND
VCC
Y
5
4
3D3V_S0
1D05V_VTT
DY
1
C503
Do Not Stuff
1
DY
R512
Do Not Stuff
XDP_BPM0
XDP_BPM1
XDP_BPM2
XDP_BPM3
XDP_BPM4
XDP_BPM5
XDP_BPM6
XDP_BPM7
XDP_TDO
XDP_TDI
XDP_TRST#
XDP_TCLK
XDP_TMS
2
1
BUF_CPU_RST#
XDP_DBRESET#
B
XDP_TDO 11
XDP_TDI 11
XDP_TRST# 11
XDP_TCLK 11
XDP_TMS 11
XDP_DBRESET# 11,19
2
,18,27,31,35,36,65,66,71,83,97
PLT_RST#
BUFO_CPU_RST#
2
1
R510
1K5R2F-2-GP
Do Not Stuff
R517
1
2
0R2J-2-GP
2
R509
750R2F-GP
A
BOM
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
CPU (THERMAL/CLOCK/PM )
Document Number
Tuesday, March 29, 2011
Rev
LZ57
Sheet
5
of
-1
102

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