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PowerPC™ Microprocessor Family:
The Programmer’s Reference Guide
©
Motorola Inc. 1995
Portions hereof
©
International Business Machines Corp. 1991–1995. All rights reserved.
This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or
discontinue this product without notice. Information in this document is provided solely to enable system and software implementers to use PowerPC
microprocessors. There are no express or implied copyright or patent licenses granted hereunder by Motorola or IBM to design, modify the design of, or
fabricate circuits based on the information in this document.
The PowerPC 60x microprocessors embody the intellectual property of Motorola and of IBM. However, neither Motorola nor IBM assumes any
responsibility or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party or by
any third party. Neither Motorola nor IBM is to be considered an agent or representative of the other, and neither has assumed, created, or granted hereby
any right or authority to the other, or to any third party, to assume or create any express or implied obligations on its behalf. Information such as data
sheets, as well as sales terms and conditions such as prices, schedules, and support, for the product may vary as between parties selling the product.
Accordingly, customers wishing to learn more information about the products as marketed by a given party should contact that party.
Both Motorola and IBM reserve the right to modify this manual and/or any of the products as described herein without further notice.
NOTHING IN THIS
MANUAL, NOR IN ANY OF THE ERRATA SHEETS, DATA SHEETS, AND OTHER SUPPORTING DOCUMENTATION, SHALL BE INTERPRETED AS
THE CONVEYANCE BY MOTOROLA OR IBM OF AN EXPRESS WARRANTY OF ANY KIND OR IMPLIED WARRANTY, REPRESENTATION, OR
GUARANTEE REGARDING THE MERCHANTABILITY OR FITNESS OF THE PRODUCTS FOR ANY PARTICULAR PURPOSE.
Neither Motorola nor
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as to the products described herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between the
marketing party and the customer. In the absence of such an agreement, no liability is assumed by Motorola, IBM, or the marketing party for any damages,
actual or otherwise.
“Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals,” must be validated for each customer
application by customer’s technical experts. Neither Motorola nor IBM convey any license under their respective intellectual property rights nor the rights
of others. Neither Motorola nor IBM makes any claim, warranty, or representation, express or implied, that the products described in this manual are
designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support
or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. Should
customer purchase or use the products for any such unintended or unauthorized application, customer shall indemnify and hold Motorola and IBM and
their respective officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that Motorola or IBM was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
IBM and IBM logo are registered trademarks, and IBM Microelectronics is a trademark of International Business Machines Corp.
The PowerPC name, PowerPC logotype, and PowerPC 601 are trademarks of International Business Machines Corp. used by Motorola under license
from International Business Machines Corp. International Business Machines Corp. is an Equal Opportunity/Affirmative Action Employer.
This document was created with FrameMaker 4.0.4
Introduction
The primary objective of this document is to provide a concise method by which system
software and hardware developers and application programmers may more readily provide
software that is compatible across the family of PowerPC processors and other devices. A
more detailed account of the following topics or the PowerPC architecture in general, may
be obtained from the
PowerPC Microprocessor Family: The Programming Environments,
referred to as
The Programming Environments Manual.
(The
PowerPC Architecture: A
Specification for a New Family of RISC Processors
defines the architecture from the
perspective of the three programming environments and remains the defining document for
the PowerPC architecture.)
This document is divided into four parts:
•
Part 1, “Register Summary,” on page 4 provides a brief overview of the PowerPC
register set, including a programming model and quick reference guides for both 32-
and 64-bit registers.
Part 2, “Memory Control Model,” on page 28 provides a brief outline of the page
table entry and segment table entry for both 32- and 64-bit implementations.
Part 3, “Exception Vectors,” on page 40 provides a quick reference for exception
types and the conditions that cause them.
Part 4, “PowerPC Instruction Set,” on page 41 provides detailed information on the
instruction field summary—including syntax and notation conventions. Also
included, is the entire PowerPC instruction set, sorted by mnemonic and opcode.
•
•
•
In this document, the term “60x” is used to denote a 32-bit microprocessor from the
PowerPC architecture family. 60x processors implement the PowerPC architecture as it is
specified for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer
data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits (single-
precision and double-precision).
Table 1 contains acronyms and abbreviations that are used in this document. Note that the
meanings for some acronyms (such as SDR1 and XER) are historical, and the words for
which an acronym stands may not be intuitively obvious.
PowerPC Microprocessor Family: The Programmer’s Reference Guide
1
This document was created with FrameMaker 4.0.4
Table 1. Acronyms and Abbreviated Terms
Term
ASR
BAT
BUID
CR
CTR
DAR
DBAT
DEC
DSISR
DTLB
EA
EAR
FPR
FPSCR
GPR
IBAT
IEEE
IU
LR
MMU
msb
MSR
NaN
No-Op
OEA
PTE
PTEG
PVR
RISC
SDR1
SIMM
SLB
Address space register
Block address translation
Bus unit ID
Condition register
Count register
Data address register
Data BAT
Decrementer register
Register used for determining the source of a DSI exception
Data translation lookaside buffer
Effective address
External access register
Floating-point register
Floating-point status and control register
General-purpose register
Instruction BAT
Institute of Electrical and Electronics Engineers
Integer unit
Link register
Memory management unit
Most significant bit
Machine state register
Not a number
No operation
Operating environment architecture
Page table entry
Page table entry group
Processor version register
Reduced instruction set computing
Register that specifies the page table base address for virtual-to-physical address translation
Signed immediate value
Segment lookaside buffer
Meaning
2
PowerPC Microprocessor Family: The Programmer’s Reference Guide
Table 1. Acronyms and Abbreviated Terms (Continued)
Term
SPR
SPRG
n
SR
SRR0
SRR1
TB
TLB
UIMM
UISA
VEA
XER
Special-purpose register
Registers available for general purposes
Segment register
Machine status save/restore register 0
Machine status save/restore register 1
Time base register
Translation lookaside buffer
Unsigned immediate value
User instruction set architecture
Virtual environment architecture
Register used for indicating conditions such as carries and overflows for integer operations
Meaning
Table 2 describes instruction field notation conventions used in this document.
Table 2. Instruction Field Conventions
The Architecture Specification
BA, BB, BT
BF, BFA
D
DS
FLM
FRA, FRB, FRC, FRT, FRS
FXM
RA, RB, RT, RS
SI
U
UI
/, //, ///
Equivalent to:
crbA, crbB, crbD
(respectively)
crfD, crfS
(respectively)
d
ds
FM
frA, frB, frC, frD, frS
(respectively)
CRM
rA, rB, rD, rS
(respectively)
SIMM
IMM
UIMM
0...0 (shaded)
PowerPC Microprocessor Family: The Programmer’s Reference Guide
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