RAM62256.pdf

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KM62256C Family
Document Title
32Kx8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No
0.0
0.1
1.0
2.0
History
Advance information
Initial draft
Finalize
Revise
- Add 45ns part with 30pF test load
Revise
- Change specification format and merge :
Commercial, Extended, Industrial product in same datasheets.
Revise
- Change Speed bin
Erase 45ns part from commercial product and 100ns from
extended and industrial product.
- Production change
Erase Low power product from TSOP package
Draft Data
February 12th 1993
November 2nd 1993
September 24th 1994
August 12th 1995
Remark
Design target
Preliminary
Final
Final
3.0
April 15th 1996
Final
4.0
December 19 1997
Final
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications and product. SAMSUNG Electronics will evaluate and reply to your requests and questions about
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
1
Revision 4.0
December 1997
KM62256C Family
32Kx8 bit Low Power CMOS Static RAM
FEATURES
•
Process Technology : 0.7µm CMOS
•
Organization : 32Kx8
•
Power Supply Voltage : Single 5V±10%
•
Low Data Retention Voltage : 2V(Min)
•
Three state output and TTL Compatible
•
Package Type : 28-DIP-600, 28-SOP-450,
28-TSOP1 -0813.4F/R
CMOS SRAM
GENERAL DESCRIPTION
The KM62256C family is fabricated by SAMSUNG′s advanced
CMOS process technology. The family supports various operat-
ing temperature ranges and has various package types for user
flexibility of system design. The family also support low data
retention voltage for battery back-up operation with low data
retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
KM62256CL
KM62256CL-L
KM62256CLE
KM62256CLE-L
KM62256CLI
KM62256CLI-L
Industrial (-40~85°C)
70ns
Extended (-25~85°C)
70ns
Operating Temperature.
Speed(ns)
PKG Type
Standby
(I
SB1
, Max)
100µA
20µA
100µA
50µA
100µA
50µA
70mA
Operating
(Icc
2
)
Commercial (0~70°C)
55/70ns
28-DIP, 28-SOP
28-TSOP I R/F
28-SOP
28-TSOP I R/F
28-SOP
28-TSOP I R/F
PIN DESCRIPTION
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A3
A4
A5
A6
A7
A12
A14
VCC
WE
A13
A8
A9
A11
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
14
13
12
11
10
9
8
7
6
5
4
3
2
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A2
A1
A0
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS
A10
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
VCC
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
28-TSOP
Type I - Forward
A3
A4
A5
A6
A7
A8
A12
A13
A14
Row
select
28-DIP
22
28-SOP
21
20
19
18
17
16
15
Memory array
512 rows
64×8 columns
28-TSOP
Type I - Reverse
I/O
1
I/O
8
Data
cont
I/O Circuit
Column select
Data
cont
NameName
A
0
~A
14
WE
CS
OE
I/O
1
~I/O
8
Vcc
Vss
Function
Address Inputs
Write Enable Input
Chip Select Input
Output Enable Input
Data Inputs/Outputs
Power(5V)
Ground
CS
WE
OE
A0
A1
A2
A9
A10
A11
Control
Logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 4.0
December 1997
KM62256C Family
PRODUCT LIST
Commercial Temp Product
(0~70°C)
Part Name
KM62256CLP-5
KM62256CLP-5L
KM62256CLP-7
KM62256CLP-7L
KM62256CLG-5
KM62256CLG-5L
KM62256CLG-7
KM62256CLG-7L
KM62256CLTG-5L
KM62256CLTG-7L
KM62256CLRG-5L
KM62256CLRG-7L
CMOS SRAM
Extended Temp Products
(-25~85°C)
Part Name
Function
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP F, 70ns, LL-pwr
28-TSOP R, 70ns, LL-pwr
Industrial Temp Products
(-40~85°C)
Part Name
KM62256CLGI-7
KM62256CLGI-7L
KM62256CLTGI-7L
KM62256CLRGI-7L
Function
Function
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP F, 70ns, LL-pwr
28-TSOP R, 70ns, LL-pwr
KM62256CLGE-7
28-DIP, 55ns, L-pwr
KM62256CLGE-7L
28-DIP, 55ns, LL-pwr
KM62256CLTGE-7L
28-DIP, 70ns, L-pwr
KM62256CLRGE-7L
28-DIP, 70ns, LL-pwr
28-SOP, 55ns, L-pwr
28-SOP, 55ns, LL-pwr
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP F, 55ns, LL-pwr
28-TSOP F, 70ns, LL-pwr
28-TSOP R, 55ns, LL-pwr
28-TSOP R, 70ns, LL-pwr
Note : LL means Low Low standby current.
FUNCTIONAL DESCRIPTION
CS
H
L
L
L
1. X means don′t care
OE
X
H
L
X
WE
X
H
H
L
I/O Pin
High-Z
High-Z
Dout
Din
Mode
Deselected
Output Disabled
Read
Write
Power
Standby
Active
Active
Active
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
1)
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
Ratings
-0.5 to V
CC
+0.5
-0.5 to 7.0
1.0
-65 to 150
0 to 70
Unit
V
V
W
°C
°C
°C
°C
-
Remark
-
-
-
-
KM62256CL
KM62256CLE
KM62256CLI
-
Operating Temperature
T
A
-25 to 85
-40 to 85
Soldering temperature and time
T
SOLDER
260°C, 10sec(Lead Only)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional oper
ation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect d vice reliability.
e
3
Revision 4.0
December 1997
KM62256C Family
RECOMMENDED DC OPERATING CONDITIONS
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Min
4.5
0
2.2
-0.5
3)
1)
CMOS SRAM
Typ
5.0
0
-
-
Max
5.5
0
Vcc+0.5V
2)
0.8
Unit
V
V
V
V
Note
1. Commercial Product : T
A
=0 to 70°C, unless otherwise specified
Extended Product : T
A
=-25 to 85°C, unless otherwise specified
Industrial Product : T
A
=-40 to 85°C, unless otherwise specified
2. Overshoot : V
CC
+3.0V in case of pulse width≤30ns
3. Undershoot : -3.0V in case of pulse width≤30ns
4. Overshoot and undershoot is sampled, not 100% tested
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
6
8
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Average operating current
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
KM62256CL
KM62256CL-L
Standby Current
(CMOS)
KM62256CLE
KM62256CLE-L
KM62256CLI
KM62256CLI-L
1. 20mA for Extended and Industrial Products
2. 10mA for Extended and Industrial Products
3. 2mA for Extended and Industrial Products
Test Conditions
V
IN
=Vss to Vcc
CS=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
Cycle time=1µs, 100% duty, I
IO
=0mA
CS≤0.2V, V
IN
≤0.2V,
V
IN
≥Vcc
-0.2V
Cycle time=Min,100% duty, I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
Min
-1
-1
-
-
-
-
2.4
-
L(Low Power)
LL(L Low Power)
-
-
-
-
-
-
Typ
-
-
7
-
-
-
-
-
2
1
-
-
-
-
Max
1
1
15
1)
7
2)
70
0.4
-
1
3)
100
20
100
50
100
50
Unit
µA
µA
mA
mA
mA
V
V
mA
µA
µA
µA
V
OL
V
OH
I
SB
I
OL
=2.1mA
I
OH
=-1.0mA
CS=V
IH
, Other inputs=V
IH
or V
IL
I
SB1
CS≥Vcc-0.2V,
Other inputs=0~Vcc
L(Low Power)
LL(L Low Power)
L(Low Power)
LL(L Low Power)
4
Revision 4.0
December 1997
KM62256C Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falingl time : 5ns
input and output reference voltage : 1.5V
Output load (See right) :C
L
=100pF+1TTL
CMOS SRAM
C
L
1)
1. Including scope and jig capacitance
A
C CHARACTERISTICS
(Vcc=4.5~5.5V, KM62256C Family : T
A
=0 to 70°C, KM62256CE Family : T
A
=-25 to 85°C,
KM62256CI Family : T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
10
5
0
0
5
55
45
0
45
40
0
0
25
0
5
55ns
Max
-
55
55
25
-
-
20
20
-
-
-
-
-
-
-
20
-
-
-
Min
70
-
-
-
10
5
0
0
5
70
60
0
60
50
0
0
30
0
5
70ns
Max
-
70
70
35
-
-
30
30
-
-
-
-
-
-
-
25
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
V
DR
KM62256CL
KM62256CL-L
Data retention current
I
DR
KM62256CLE
KM62256CLE-L
KM62256CLI
KM62256CLI-L
Data retention set-up time
Recovery time
t
SDR
t
RDR
Vcc=3.0V
CS≥Vcc-0.2V
Symbol
Test Condition
CS≥Vcc-0.2V
L-Ver
LL-Ver
L-Ver
LL-Ver
L-Ver
LL-Ver
See data retention waveform
Min
2.0
-
-
-
-
-
-
0
5
Typ
-
1
0.5
-
-
-
-
-
-
Max
5.5
50
10
50
25
50
25
-
-
ms
µA
Unit
V
5
Revision 4.0
December 1997

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