M48T08.PDF

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M48T08
M48T18
64 Kbit (8Kb x 8) TIMEKEEPER
®
SRAM
INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
BYTEWIDE™ RAM-LIKE CLOCK ACCESS
BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES and SECONDS
TYPICAL CLOCK ACCURACY of
±
1 MINUTE
a MONTH, at 25°C
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
– M48T08: 4.5V
≤
V
PFD
≤
4.75V
– M48T18: 4.2V
≤
V
PFD
≤
4.5V
SOFTWARE CONTROLLED CLOCK
CALIBRATION for HIGH ACCURACY
APPLICATIONS
SELF-CONTAINED BATTERY and CRYSTAL in the
CAPHAT DIP PACKAGE
PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT
®
TOP
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
PIN and FUNCTION COMPATIBLE with
DS1643 and JEDEC STANDARD 8K x 8
SRAMs
SNAPHAT (SH)
Battery/Crystal
28
28
1
1
SOH28 (MH)
PCDIP28 (PC)
Battery/Crystal
CAPHAT
Figure 1. Logic Diagram
VCC
13
A0-A12
8
DQ0-DQ7
Table 1. Signal Names
A0-A12
DQ0-DQ7
INT
E1
E2
G
W
V
CC
V
SS
May 1999
Address Inputs
W
E1
M48T08
M48T18
INT
Data Inputs / Outputs
Power Fail Interrupt (Open Drain)
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Supply Voltage
Ground
1/19
E2
G
VSS
AI01020
M48T08, M48T18
Figure 2A. DIP Pin Connections
INT
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
28
1
27
2
26
3
25
4
24
5
23
6
7
M48T08 22
8
M48T18 21
20
9
19
10
18
11
17
12
13
16
14
15
AI01182
Figure 2B. SOIC Pin Connections
VCC
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
INT
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
27
2
26
3
25
4
24
5
23
6
22
7
M48T18
21
8
20
9
19
10
18
11
17
12
16
13
15
14
AI01021B
VCC
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
T
SLD (2)
V
IO
V
CC
I
O
P
D
Parameter
Ambient Operating Temperature
Storage Temperature (V
CC
Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
Supply Voltage
Output Current
Power Dissipation
Value
0 to 70
–40 to 85
260
–0.3 to 7
–0.3 to 7
20
1
Unit
°C
°C
°C
V
V
mA
W
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION:
Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION:
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 3. Operating Modes
Mode
Deselect
Deselect
Write
Read
Read
Deselect
Deselect
V
SO
to V
PFD
(min)
≤
V
SO
4.75V to 5.5V
or
4.5V to 5.5V
V
CC
E1
V
IH
X
V
IL
V
IL
V
IL
X
X
E2
X
V
IL
V
IH
V
IH
V
IH
X
X
G
X
X
X
V
IL
V
IH
X
X
W
X
X
V
IL
V
IH
V
IH
X
X
DQ0-DQ7
High Z
High Z
D
IN
D
OUT
High Z
High Z
High Z
Power
Standby
Standby
Active
Active
Active
CMOS Standby
Battery Back-up Mode
Notes:
1. X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
2/19
M48T08, M48T18
Figure 3. Block Diagram
OSCILLATOR AND
CLOCK CHAIN
32,768 Hz
CRYSTAL
POWER
8 x 8 BiPORT
SRAM ARRAY
A0-A12
8184 x 8
SRAM ARRAY
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
VPFD
DQ0-DQ7
E1
E2
W
G
VCC
INT
VSS
AI01333
DESCRIPTION
The M48T08/18 TIMEKEEPER
®
RAM is an 8K x 8
non-volatile static RAM and real time clock which
is pin and functional compatible with the DS1643.
The monolithic chip is available in two special
packages to provide a highly integrated battery
backed-up memory and real time clock solution.
The M48T08/18 is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The 28 pin 600mil DIP CAPHAT™ houses the
M48T08/18 silicon with a quartz crystal and a long
life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery and crystal. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery and
crystal damage due to the high temperatures re-
quired for device surface-mounting. The SNAPHAT
housing is keyed to prevent reverse insertion.
Table 4. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
5ns
0 to 3V
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 4. AC Testing Load Circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
1kΩ
OUT
CL = 100pF
CL includes JIG capacitance
AI01019
3/19
M48T08, M48T18
Table 5. Capacitance
(1, 2)
(T
A
= 25
°C,
f = 1 MHz )
Symbol
C
IN
C
IO (3)
Parameter
Input Capacitance
Input / Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
10
10
Unit
pF
pF
Notes:
1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(T
A
= 0 to 70°C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
I
LI (1)
I
LO (1)
I
CC
I
CC1 (2)
I
CC2 (2)
V
IL(3)
V
IH
V
OL
V
OH
Notes:
1.
2.
3.
4.
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage (INT)
(4)
Output High Voltage
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
Outputs open
E1 = V
IH
, E2 = V
IL
E1 = V
CC
– 0.2V,
E2 = V
SS
+ 0.2V
Min
Max
±1
±5
80
3
3
Unit
µA
µA
mA
mA
mA
V
V
V
V
V
–0.3
2.2
I
OL
= 2.1mA
I
OL
= 0.5mA
I
OH
= –1mA
2.4
0.8
V
CC
+ 0.3
0.4
0.4
Outputs Deselected.
Measured with Control Bits set as follows: R = ’1’; W, ST, FT = ’0’.
Negative spikes of –1V allowed for up to 10ns once per Cycle.
The INT pin is Open Drain.
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70°C)
Symbol
V
PFD
V
PFD
V
SO
t
DR(2)
Parameter
Power-fail Deselect Voltage (M48T08)
Power-fail Deselect Voltage (M48T18)
Battery Back-up Switchover Voltage
Expected Data Retention Time
10
Min
4.5
4.2
Typ
4.6
4.3
3.0
Max
4.75
4.5
Unit
V
V
V
YEARS
Notes:
1. All voltages referenced to V
SS
.
2. At 25°C
DESCRIPTION
(cont’d)
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28 lead SOIC, the
battery/crystal package (i.e. SNAPHAT) part num-
ber is "M4T28-BR12SH1".
As Figure 3 shows, the static memory array and the
quartz controlled clock oscillator of the M48T08/18
are integrated on one silicon chip. The two circuits
are interconnected at the upper eight memory lo-
cations to provide user accessible BYTEWIDE™
clock information in the bytes with addresses
1FF8h-1FFFh.
4/19
M48T08, M48T18
Table 8. Power Down/Up Mode AC Characteristics
(T
A
= 0 to 70°C)
Symbol
t
PD
t
F (1)
t
FB (2)
t
R
t
RB
t
REC
t
PFX
t
PFH(3)
Parameter
E1 or W at V
IH
or E2 at V
IL
before Power Down
V
PFD
(max) to V
PFD
(min) V
CC
Fall Time
V
PFD
(min) to V
SO
V
CC
Fall Time
V
PFD
(min) to V
PFD
(max) V
CC
Rise Time
V
SO
to V
PFD
(min) V
CC
Rise Time
E1 or W at V
IH
or E2 at V
IL
after Power Up
INT Low to Auto Deselect
V
PFD
(max) to INT High
Min
0
300
10
0
1
1
10
40
120
Max
Unit
µs
µs
µs
µs
µs
ms
µs
µs
Notes:
1. V
PFD
(max) to V
PFD
(min) fall time of less than t
F
may result in deselection/write protection not occurring until 200
µs
after
V
CC
passes V
PFD
(min).
2. V
PFD
(min) to V
SO
fall time of less than t
FB
may cause corruption of RAM data.
3. INT may go high anytime after V
CC
exceeds V
PFD
(min) and is guaranteed to go high t
PFH
after V
CC
exceeds V
PFD
(max).
Figure 5. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tPD
tFB
tPFX
INT
tREC
INPUTS
RECOGNIZED
tDR
tRB
tR
tPFH
DON'T CARE
NOTE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI00566
Note:
Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high or E2 low as V
CC
rises past V
PFD
(min).
Some systems may perform inadvertent write cycles after V
CC
rises above V
PFD
(min) but before normal system operations begin. Even
though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is runn ing.
5/19

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