1386P.PDF

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DS1386/DS1386P
RAMified Watchdog Timekeeper
www.dalsemi.com
FEATURES
§
8 or 32 kbytes of user NV RAM
§
Integrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
§
Totally nonvolatile with over 10 years of
operation in the absence of power
§
Watchdog timer restarts an out-of-control
processor
§
Alarm function schedules real-time related
activities such as system wakeup
§
Programmable interrupts and square wave
output
§
All registers are individually addressable via
the address and data bus
§
Interrupt signals are active in power-down
mode
INTA
INTB
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN ASSIGNMENT
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
SQW
V
CC
WE
NC
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
INTA
INTB
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
SQW
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DS1386 128K x 8
32-PIN ENCAPSULATED
PACKAGE
DS1386 128K x 8
32-PIN ENCAPSULATED
PACKAGE
INTB(INTB)
NC
NC
PFO
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
X1
GND V
BAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
INTA
SQW
NC
NC
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
INTB(INTB)
NC
NC
PFO
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
X1
GND V
BAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
INTA
SQW
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DS1386 8K x 8
34-PIN POWERCAP MODULE BOARD
(USES DS9034PCX POWERCAP)
(USES DS9034PCX POWERCAP)
DS1386 32K x 8
34-PIN POWERCAP MODULE BOARD
(USES DS9034PCX POWERCAP)
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DS1386/DS1386P
ORDERING INFORMATION
DS1386
XX-XXX
32-pin DIP Module
-150
-120
08
32
*DS1386P
XX-XXX
150 ns access
120 ns access
8K x 8 NVSRAM
32K x 8 NVSRAM
34-pin PowerCap Module Board
-150
-120
08
32
150 ns access
120 ns access
8K x 8 NVSRAM
32K x 8 NVSRAM
*DS9034PCX
PowerCap required
(must be ordered separately)
PIN DESCRIPTION
INTA
INTB
(INTB)
A0-A14
DQ0-DQ7
CE
OE
WE
V
CC
GND
SQW
NC
X1, X2
V
BAT
- Interrupt Output A (open drain)
- Interrupt Output B (open drain)
- Address Inputs
- Data Input/Output
- Chip Enable
- Output Enable
- Write Enable
- +5 Volts
- Ground
- Square Wave Output
- No Connection
- Crystal Connection
- Battery Connection
DESCRIPTION
The DS1386 is a nonvolatile static RAM with a full-function Real Time Clock (RTC), alarm, watchdog
timer, and interval timer which are all accessible in a byte-wide format. The DS1386 contains a lithium
energy source and a quartz crystal, which eliminates the need for any external circuitry. Data contained
within 8K or 32K by 8-bit memory and the timekeeping registers can be read or written in the same
manner as bytewide static RAM. The timekeeping registers are located in the first 14 bytes of memory
space. Data is maintained in the RAMified Timekeeper by intelligent control circuitry which detects the
status of V
CC
and write protects memory when V
CC
is out of tolerance. The lithium energy source can
maintain data and real time for over ten years in the absence of V
CC
. Timekeeper information includes
hundredths of seconds, seconds, minutes, hours, day, date, month, and year. The date at the end of the
month is automatically adjusted for months with less than 31 days, including correction for leap year.
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DS1386/1386P
The RAMified Timekeeper operates in either 24-hour or 12-hour format with an AM/PM indicator. The
watchdog timer provides alarm interrupts and interval timing between 0.01seconds and 99.99 seconds.
The real time alarm provides for preset times of up to one week. Interrupts for both watchdog and RTC
will operate when system is powered down. Either can provide system “wake-up” signals.
PACKAGES
The DS1386 is available in two packages (32-pin DIP module and 34-pin PowerCap module). The 32-pin
DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1386P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
OPERATION - READ REGISTERS
The DS1386 executes a read cycle whenever
WE
(Write Enable) is inactive (High),
CE
(Chip Enable)
and
OE
(Output Enable) are active (Low). The unique address specified by the address inputs (A0-A14)
defines which of the registers is to be accessed. Valid data will be available to the eight data output
drivers within t
ACC
(Access Time) after the last address input signal is stable, providing that
CE
and
OE
access times are also satisfied. If
OE
and
CE
access times are not satisfied, then data access must be
measured from the latter occurring signal (
CE
or
OE
) and the limiting parameter is either t
CO
for
CE
or
t
OE
for
OE
rather than address access.
OPERATION - WRITE REGISTERS
The DS1386 is in the write mode whenever the
WE
(Write Enable) and
CE
(Chip Enable) signals are in
the active (Low) state after the address inputs are stable. The latter occurring falling edge of
CE
or
WE
will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be kept valid throughout the write cycle.
WE
must return to the high state
for a minimum recovery state (t
WR
) before another cycle can be initiated. Data must be valid on the data
bus with sufficient Data Set-Up (t
DS
) and Data Hold Time (t
DH
) with respect to the earlier rising edge of
CE
or
WE
. The
OE
control signal should be kept inactive (High) during write cycles to avoid bus
contention. However, if the output bus has been enabled (
CE
and
OE
active), then
WE
will disable the
outputs in t
ODW
from its falling edge.
DATA RETENTION
The RAMified Timekeeper provides full functional capability when V
CC
is greater than 4.5 volts and
write-protects the register contents at 4.25 volts typical. Data is maintained in the absence of V
CC
without
any additional support circuitry. The DS1386 constantly monitors V
CC
. Should the supply voltage decay,
the RAMified Timekeeper will automatically write-protect itself and all inputs to the registers become
“don’ care.” The two interrupts
INTA
and
INTB
(INTB) and the internal clock and timers continue to run
t
regardless of the level of V
CC
. However, it is important to insure that the pullup resistors used with the
interrupt pins are never pulled up to a value that is greater than V
CC
+ 0.3V. As V
CC
falls below
approximately 3.0 volts, a power switching circuit turns the internal lithium energy source on to maintain
the clock and timer data and functionality. It is also required to insure that during this time (battery
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DS1386/1386P
backup mode), the voltage present at
INTA
and
INTB
(INTB) never exceeds 3.0V. During power-up,
when V
CC
rises above approximately 3.0 volts, the power switching circuit connects external V
CC
and
disconnects the internal lithium energy source. Normal operation can resume after V
CC
exceeds 4.5 volts
for a period of 200 ms.
RAMIFIED TIMEKEEPER REGISTERS
The RAMified Timekeeper has 14 registers which are 8 bits wide that contain all of the timekeeping,
alarm, watchdog and control information. The clock, calendar, alarm, and watchdog registers are memory
locations which contain external (user-accessible) copies of the timekeeping data. The external copies are
independent of internal functions except that they are updated periodically by the simultaneous transfer of
the incremented internal copy (see Figure 1). The Command Register bits are affected by both internal
and external functions. This register will be discussed later. The 8 or 32 kbytes of RAM and the 14
external timekeeping registers are accessed from the external address and data bus. Registers 0, 1, 2, 4, 6,
8, 9, and A contain time of day and date information (see Figure 2). Time of day information is stored in
BCD. Registers 3, 5, and 7 contain the Time of Day Alarm information. Time of Day Alarm information
is stored in BCD. Register B is the Command Register and information in this register is binary. Registers
C and D are the Watchdog Alarm Registers and information which is stored in these two registers is in
BCD. Registers E through 1FFF or 7FFF are user bytes and can be used to maintain data at the user’
s
discretion.
CLOCK ACCURACY (DIP MODULE)
The DS1386 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1386P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within
±1.53
minutes per month (35 ppm) at 25°
C.
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DS1386/1386P
BLOCK DIAGRAM
Figure 1
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