21Q43A.PDF

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DS21Q43A
Quad E1 Framer
www.dalsemi.com
FEATURES
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Four E1 (CEPT or PCM-30) /ISDN-PRI
framing transceivers
All four framers are fully independent;
transmit and receive sections of each framer
are fully independent
Frames to FAS, CAS, CCS, and CRC4
formats
8-bit parallel control port that can be
connected to either multiplexed or non-
multiplexed buses
Each of the four framers contains dual two-
frame elastic stores that can connect to
asynchronous or synchronous backplanes up
to 8.192 MHz
Easy access to Si and Sa bits
Extracts and inserts CAS signaling
Large counters for bipolar and code
violations, CRC4 code word errors, FAS
word errors, and E-bits
Programmable output clocks for Fractional
E1, per channel loopback, H0 and H12
applications
Detects and generates AIS, remote alarm, and
remote multiframe alarms
Pin-compatible with DS21Q41B Quad T1
Framer
5V supply; low power CMOS
Available in 128-pin TQFP
Industrial (-40°C to +85°C) grade version
available (DS21Q43ATN)
FUNCTIONAL DIAGRAM
RECEIVE
FRAMER
ELASTIC
STORE
TRANSMIT
FORMATTER
ELASTIC
STORE
FRAMER #0
FRAMER #1
FRAMER #2
FRAMER #3
CONTROL PORT
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ACTUAL SIZE
QUAD
E1
FRAMER
DESCRIPTION
The DS21Q43A combines four of the popular DS2143 E1 Controllers onto a single monolithic die. The
“A” designation denotes that some new features are available in the Quad version which were not
available in the single E1 device. The added features in the DS21Q43A are listed in Section 1. The
DS21Q43A offers a substantial space savings to applications that require more than one E1 framer on a
card. The Quad version is only slightly bigger than the single E1 device. All four framers in the
DS21Q43A are totally independent; they do not share a common framing synchronizer. Also, the transmit
and receive sides of each framer are totally independent. The dual two-frame elastic stores contained in
each of the four framers can be independently enabled and disabled as required. The DS21Q43A meets
all of the latest specifications, including CCITT/ITU G.704, G.706, G.962, and I.431 as well as ETS 300
011 and ETS 300 233.
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092299
DS21Q43A
1.0 INTRODUCTION
The DS21Q43A Quad E1 Framer is made up of five main parts: framer #0, framer #1, framer #2, framer
#3, and the control port which is shared by all four framers. See the Block Diagram in Figure 1-1. Each
of the four framers within the DS21Q43A maintains the same register structure that appeared in the
DS2143. The two framer-select inputs (FS0 and FS1) are used to determine which framer within the
DS21Q43A is being accessed. In this manner, software written for the DS2143 can also be used in the
DS21Q43A with only slight modifications. Several new features have been added to the framers in the
DS21Q43A over the DS2143.
ADDED FEATURE
Non-multiplexed parallel control port operation
Transmit side elastic store
Expanded access to Sa and Si bits
Control signals RFSYNC, RMSYNC, and TFSYNC
FAS word error counting
Code violation counting
Automatic AIS generation upon loss of frame sync
Automatic remote alarm generation
Per-channel signaling insertion
Per-channel loopback from RSER to TSER
Option to update error counters every 62.5 ms
CRC4 resync criteria met status bit
Elastic store reset
Hardware 3-state control
SECTION
2 and 13
10
6
1
5
5
3
3
9 and 11
8 and 11
5
4
10
1
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DS21Q43A
DS21Q43A BLOCK DIAGRAM
Figure 1-1
READER’S NOTE
This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit
timeslots in an E1 system which are numbered 0 to 31. Timeslot 0 is transmitted first and received first.
These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is
identical to channel 1, timeslot 1 is identical to channel 2, and so on. Each timeslot (or channel) is made
up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is
the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:
FAS
CAS
MF
Si
Frame Alignment
Channel Associated
Signaling
Multiframe
International bits
CRC4
CCS
Sa
E-bit
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Cyclical Redundancy Check
Common Channel Signaling
Additional bits
CRC4 Error bits
DS21Q43A
PIN-OUT CONFIGURATION
Figure 1-2
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DS21Q43A
TRANSMIT PIN LIST
Table 1-1
PIN
19
53
87
113
126
32
66
92
128
34
68
94
1
35
69
95
20
54
88
114
22
56
90
116
2
36
70
96
3
37
71
97
21
55
89
115
SYMBOL
TCLK0
TCLK1
TCLK2
TCLK3
TSER0
TSER1
TSER2
TSER3
TCHCLK0
TCHCLK1
TCHCLK2
TCHCLK3
TCHBLK0
TCHBLK1
TCHBLK2
TCHBLK3
TLCLK0
TLCLK1
TLCLK2
TLCLK3
TLINK0
TLINK1
TLINK2
TLINK3
TPOS0
TPOS1
TPOS2
TPOS3
TNEG0
TNEG1
TNEG2
TNEG3
TSYNC0
TSYNC1
TSYNC2
TSYNC3
TYPE
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
DESCRIPTION
Transmit Clock for Framer 0
Transmit Clock for Framer 1
Transmit Clock for Framer 2
Transmit Clock for Framer 3
Transmit Serial Data for Framer 0
Transmit Serial Data for Framer 1
Transmit Serial Data for Framer 2
Transmit Serial Data for Framer 3
Transmit Channel Clock from Framer 0
Transmit Channel Clock from Framer 1
Transmit Channel Clock from Framer 2
Transmit Channel Clock from Framer 3
Transmit Channel Block from Framer 0
Transmit Channel Block from Framer 1
Transmit Channel Block from Framer 2
Transmit Channel Block from Framer 3
Transmit Link Clock from Framer 0
Transmit Link Clock from Framer 1
Transmit Link Clock from Framer 2
Transmit Link Clock from Framer 3
Transmit Link Data for Framer 0
Transmit Link Data for Framer 1
Transmit Link Data for Framer 2
Transmit Link Data for Framer 3
Transmit Bipolar Data from Framer 0
Transmit Bipolar Data from Framer 1
Transmit Bipolar Data from Framer 2
Transmit Bipolar Data from Framer 3
Transmit Bipolar Data from Framer 0
Transmit Bipolar Data from Framer 1
Transmit Bipolar Data from Framer 2
Transmit Bipolar Data from Framer 3
Transmit Sync for Framer 0
Transmit Sync for Framer 1
Transmit Sync for Framer 2
Transmit Sync for Framer 3
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