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DS2152
Enhanced T1 Single-Chip Transceiver
www.dalsemi.com
FEATURES
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Complete DS1/ISDN-PRI transceiver
functionality
Line interface can handle both long and short haul
trunks
32-bit or 128-bit crystal-less jitter attenuator
Generates DSX-1 and CSU line build outs
Frames to D4, ESF, and SLC-96
R
formats
Dual onboard two-frame elastic store slip buffers
that can connect to asynchronous backplanes up to
8.192 MHz
8-bit parallel control port that can be used directly
on either multiplexed or non-multiplexed buses
(Intel or Motorola)
Extracts and inserts robbed-bit signaling
Detects and generates yellow (RAI) and blue
(AIS) alarms
Programmable output clocks for Fractional T1
Fully independent transmit and receive
functionality
Integral HDLC controller with 16-byte buffers for
the FDL
Generates and detects in-band loop codes from 1
to 8 bits in length including CSU loop codes
Contains ANSI 1's density monitor and enforcer
Large path and line error counters including BPV,
CV, CRC6, and framing bit errors
Pin compatible with DS2154 E1 Enhanced Single-
Chip Transceiver
5V supply; low power CMOS
100-pin 14mm
2
body LQFP package
PIN ASSIGNMENT
100
1
ORDERING INFORMATION
DS2152L
DS2152LN
(0°C to 70°C)
(-40°C to +85°C)
DESCRIPTION
The DS2152 T1 Enhanced Single-Chip Transceiver contains all of the necessary functions for connection
to T1 lines, whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry
automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both
DSX-1 line build outs as well as CSU line build outs of -7.5 dB, -15 dB, and -22.5 dB. The onboard jitter
attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data
paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It
is also used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set
of internal registers which the user can access and control the operation of the unit. Quick access via the
parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the
latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12-90),
AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.
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092299
DS2152
TABLE OF CONTENTS
1.0
INTRODUCTION ..................................................................................... 4
Block Diagram...............................................................................................................................
Pin List...........................................................................................................................................
Pin Description ..............................................................................................................................
Register Map..................................................................................................................................
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7
9
13
2.0
3.0
PARALLEL PORT................................................................................... 17
CONTROL, ID, AND TEST REGISTERS ................................................ 18
Payload Loopback .........................................................................................................................
Framer Loopback...........................................................................................................................
Pulse Density Enforcer ..................................................................................................................
Local Loopback .............................................................................................................................
Power-up Sequence .......................................................................................................................
Remote Loopback..........................................................................................................................
23
23
25
27
29
29
4.0
5.0
STATUS AND INFORMATION REGISTERS .......................................... 30
ERROR COUNT REGISTERS ................................................................ 38
Line Code Violation Count Register .............................................................................................
Path Code Violation Count Register..............................................................................................
Multiframes Out of SYNC Count Register ...................................................................................
39
39
40
6.0
7.0
DSO MONITORING FUNCTION ............................................................. 41
SIGNALING OPERATION....................................................................... 44
Processor Based Signaling..........................................................................................................
Hardware Based Signaling..........................................................................................................
44
46
8.0
PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK.......... 47
Transmit Side Code Generation.....................................................................................................
Receive Side Code Generation ......................................................................................................
47
49
9.0
CLOCK BLOCKING REGISTERS .......................................................... 51
10.0 ELASTIC STORES OPERATION............................................................ 52
11.0 FDL/F
S
EXTRACTION AND INSERTION................................................ 53
HDLC and BOC Controller for the FDL.......................................................................................
Legacy FDL Support .....................................................................................................................
D4/SLC-96 Operation....................................................................................................................
53
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12.0 PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION 65
13.0 TRANSMIT TRANSPARENCY................................................................ 68
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DS2152
14.0 LINE INTERFACE FUNCTION................................................................ 69
15.0 TIMING DIAGRAMS................................................................................ 74
Transmit Data Flow Diagram ........................................................................................................ 80
16.0 CHARACTERISTICS .............................................................................. 81
Absolute Maximum Rating............................................................................................................
DC Parameters ...............................................................................................................................
AC Parameters ...............................................................................................................................
Timing............................................................................................................................................
Package Description ......................................................................................................................
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DS2152
1.0 INTRODUCTION
The DS2152 is a superset version of the popular DS2151 T1 Single-Chip Transceiver offering the new
features listed below. All of the original features of the DS2151 have been retained and software created
for the original devices is transferable into the DS2152.
New Features
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option for non-multiplexed bus operation
crystal-less jitter attenuation
additional hardware signaling capability including:
– receive signaling reinsertion to a backplane multiframe sync
– availability of signaling in a separate PCM data stream
– signaling freezing
– interrupt generated on change of signaling data
per-channel code insertion in both transmit and receive paths
full HDLC controller for the FDL with 16-byte buffers in both transmit and receive paths
RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state
8.192 MHz clock synthesizer
per-channel loopback
addition of hardware pins to indicate carrier loss & signaling freeze
line interface function can be completely decoupled from the framer/formatter to allow:
– interface to optical, HDSL, and other NRZ interfaces
– ability to “tap” the transmit and receive bipolar data streams for monitoring purposes
– ability to corrupt data and insert framing errors, CRC errors, etc.
transmit and receive elastic stores now have independent backplane clocks
ability to monitor one DS0 channel in both the transmit and receive paths
access to the data streams in between the framer/formatter and the elastic stores
AIS generation in the line interface that is independent of loopbacks
ability to calculate and check CRC6 according to the Japanese standard
ability to pass the F-bit position through the elastic stores in the 2.048 MHz backplane mode
programmable in-band loop code generator and detector
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Functional Description
The analog AMI/B8ZS waveform off the T1 line is transformer-coupled into the RRING and RTIP pins
of the DS2152. The device recovers clock and data from the analog signal and passes it through the jitter
attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the
framing/multi-frame pattern. The DS2152 contains an active filter that reconstructs the analog received
signal for the non-linear losses that occur in transmission. The device has a usable receive sensitivity of 0
dB to -36 dB, which allows the device to operate on cables up to 6000 feet in length. The receive side
framer locates D4 (SLC-96) or ESF multiframe boundaries as well as detects incoming alarms, including
carrier loss, loss of synchronization, blue (AIS) and yellow alarms. If needed, the receive side elastic store
can be enabled in order to absorb the phase and frequency differences between the recovered T1 data
stream and an asynchronous backplane clock which is provided at the RSYSCLK input. The clock
applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock. The RSYSCLK
can be a bursty clock with speeds up to 8.192 MHz.
The transmit side of the DS2152 is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
T1 transmission. Once the data stream has been prepared for transmission, it is sent via the jitter
attenuation mux to the waveshaping and line driver functions. The DS2152 will drive the T1 line from the
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DS2152
TTIP and TRING pins via a coupling transformer. The line driver can handle both long (CSU) and short
haul (DSX-1) lines.
Reader’s Note
This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125 us frame,
there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by
channel 1. Each channel is made up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is
transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the
following abbreviations will be used:
D4
SLC-96
ESF
B8ZS
CRC
Ft
Fs
FPS
MF
BOC
HDLC
FDL
Superframe (12 frames per multiframe) Multiframe Structure
Subscriber Loop Carrier - 96 Channels (SLC-96 is an AT&T registered trademark)
Extended Superframe (24 frames per multiframe) Multiframe Structure
Bipolar with 8 0 Subsitution
Cyclical Redundancy Check
Terminal Framing Pattern in D4
Signaling Framing Pattern in D4
Framing Pattern in ESF
Multiframe
Bit Oriented Code
High Level Data Link Control
Facility Data Link
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