1258Y_AB.PDF

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DS1258Y/AB
128k x 16 Nonvolatile SRAM
www.dalsemi.com
FEATURES
10-year minimum data retention in the
absence of external power
Data is automatically protected during a
power loss
Separate upper byte and lower byte chip
select inputs
Unlimited write cycles
Low-power CMOS
Read and write access times as fast as 70 ns
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
Full
±10%
operating range (DS1258Y)
Optional
±5%
operating range (DS1258AB)
PIN ASSIGNMENT
CEU
CEL
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
GND
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
WE
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
40-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
PIN DESCRIPTION
A0 - A16
DQ0 - DQ15
CEU
CEL
WE
OE
V
CC
GND
- Address Inputs
- Data In/Data Out
- Chip Enable Upper Byte
- Chip Enable Lower Byte
- Write Enable
- Output Enable
- Power (+5V)
- Ground
DESCRIPTION
The DS1258 128k x 16 Nonvolatile SRAMs are 2,097,152-bit fully static, nonvolatile SRAMs, organized
as 131,072 words by 16 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry which constantly monitors V
CC
for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. DIP-package DS1258 devices can be used in place of solutions which build
nonvolatile 128k x 16 memory by utilizing a variety of discrete components. There is no limit on the
number of write cycles that can be executed and no additional support circuitry is required for
microprocessor interfacing.
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111999
DS1258Y/AB
READ MODE
The DS1258 devices execute a read cycle whenever
WE
(Write Enable) is inactive (high) and either/both
of
CEU
or
CEL
(Chip Enables) are active (low) and
OE
(Output Enable) is active (low). The unique
address specified by the 17 address inputs (A0-A16) defines which of the 131,072 words of data is
accessed. The status of
CEU
and
CEL
determines whether all or part of the addressed word is accessed. If
CEU
is active with
CEL
inactive, then only the upper byte of the addressed word is accessed. If
CEU
is
inactive with
CEL
active, then only the lower byte of the addressed word is accessed. If both the
CEU
and
CEL
inputs are active (low), then the entire 16-bit word is accessed. Valid data will be available to
the 16 data output drivers within t
ACC
(Access Time) after the last address input signal is stable, providing
that
CEU
,
CEL
and
OE
access times are also satisfied. If
CEU
,
CEL
, and
OE
access times are not
satisfied, then data access must be measured from the later occurring signal, and the limiting parameter is
either t
CO
for
CEU
,
CEL
, or t
OE
for
OE
rather than address access.
WRITE MODE
The DS1258 devices execute a write cycle whenever
WE
and either/both of
CEU
or
CEL
are active (low)
after address inputs are stable. The unique address specified by the 17 address inputs (A0-A16) defines
which of the 131,072 words of data is accessed. The status of
CEU
and
CEL
determines whether all or
part of the addressed word is accessed. If
CEU
is active with
CEL
inactive, then only the upper byte of
the addressed word is accessed. If
CEU
is inactive with
CEL
active, then only the lower byte of the
addressed word is accessed. If both the
CEU
and
CEL
inputs are active (low), then the entire 16-bit word
is accessed. The write cycle is terminated by the earlier rising edge of
CEU
and/or
CEL
, or
WE
. All
address inputs must be kept valid throughout the write cycle.
WE
must return to the high state for a
minimum recovery time (t
WR
) before another cycle can be initiated. The
OE
control signal should be kept
inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled
(
CEU
and/or
CEL
, and
OE
active) then
WE
will disable the outputs in t
ODW
from its falling edge.
READ/WRITE FUNCTION
Table 1
OE
WE
CEL
CEU
V
CC
CURRENT
I
CCO
I
CCO
DQ0-DQ7
High-Z
Output
Output
High-Z
Input
DQ8-DQ15
High-Z
Output
High-Z
Output
Input
High-Z
Input
High-Z
CYCLE
PERFORMED
Output Disabled
Read Cycle
H
L
L
L
X
X
X
X
H
H
H
H
L
L
L
X
X
L
L
H
L
L
H
H
X
L
H
L
L
H
L
H
I
CCO
I
CCS
Input
High-Z
High-Z
Write Cycle
Output Disabled
DATA RETENTION MODE
The DS1258AB provides full functional capability for V
CC
greater than 4.75 volts, and write protects by
4.5 volts. The DS1258Y provides full functional capability for V
CC
greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of V
CC
without any additional support circuitry.
The nonvolatile static RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high
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DS1258Y/AB
impedance. As V
CC
falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when V
CC
rises above approximately 3.0 volts,
the power switching circuit connects external V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds 4.75 volts for the DS1258AB and 4.5 volts for the
DS1258Y.
FRESHNESS SEAL
The DS1258 devices are shipped from Dallas Semiconductor with the lithium energy sources
disconnected, guaranteeing full energy capacity. When V
CC
is first applied at a level greater than V
TP
, the
lithium energy source is enabled for battery backup operation.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
-0.3V to +7.0V
0°C to 70°C
-40°C to +70°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
DS1258AB Power Supply Voltage
DS1258AB Power Supply Voltage
Logic 1
Logic 0
SYMBOL
V
CC
V
CC
V
IH
V
IL
MIN
4.75
4.5
2.2
0.0
TYP
5.0
5.0
MAX
5.25
5.5
V
CC
+0.8
(t
A
: 0°C to 70°C)
UNITS
V
V
V
V
NOTES
DC ELECTRICAL
CHARACTERISTICS
PARAMETER
Input Leakage Current
I/O Leakage Current
CE
≥
V
IH
≤
V
CC
Output Current @ 2.4V
Output Current @ 0.4V
Standby Current
CEU
,
CEL
=2.2V
Standby Current
CEU
,
CEL
=V
CC
-0.5V
Operating Current
Write Protection Voltage (DS1258AB)
Write Protection Voltage (DS1258Y)
(V
CC
=5V
±=5%
for DS1258AB)
(t
A
: 0°C to 70°C) (V
CC
=5V
±=10%
for DS1258Y)
SYMBOL
I
IL
I
IO
I
OH
I
OL
I
CCS1
I
CCS2
I
CCO1
V
TP
V
TP
4.50
4.25
4.62
4.37
MIN
-2.0
-1.0
-1.0
2.0
10
6
20
10
170
4.75
4.5
TYP
MAX
+2.0
+1.0
UNITS
µA
µA
mA
mA
mA
mA
mA
V
V
NOTES
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DS1258Y/AB
CAPACITANCE
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN
TYP
20
5
MAX
25
10
(t
A
=25°C)
UNITS
pF
pF
NOTES
AC ELECTRICAL
CHARACTERISTICS
(V
CC
=5V
±=5%
for DS1258AB)
(t
A
: 0°C to 70°C) (V
CC
=5V
±=10%
for DS1258Y)
DS1258AB-70
DS1258Y-70
DS1258AB-100
DS1258Y-100
PARAMETER
Read Cycle Time
Access Time
OE
CE
OE
SYMBOL
t
RC
t
ACC
t
OE
t
CO
t
COE
t
OD
t
OH
t
WC
t
WP
t
AW
t
WR1
t
WR2
t
ODW
t
OEW
t
DS
t
DH1
t
DH2
MIN
70
MAX
70
35
70
MIN
100
MAX
100
50
100
UNITS
ns
ns
ns
ns
ns
NOTES
to Output Valid
to Output Valid
or
CE
to Output Valid
5
25
5
70
55
0
5
15
25
5
30
0
10
5
35
5
100
75
0
5
15
35
5
40
0
10
5
5
Output High Z from Deselection
Output Hold from Address Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
Output High Z from
WE
Output Active from
WE
Data Setup Time
Data Hold Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
12
13
5
5
4
12
13
READ CYCLE
SEE NOTE 1
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DS1258Y/AB
WRITE CYCLE 1
SEE NOTE 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
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