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Application Note 14
Design Considerations for
All-Silicon Delay Lines
www.dalsemi.com
SILICON DELAY LINES VS. HYBRID L-C NETWORKS
Figure 1 shows internal views of a typical 5-tap hybrid delay line and its silicon counterpart. A hybrid is
manufactured using a commercially available hex inverter DIP (e.g., 74LS04) with a small PC board
placed on top to supply a ground plane. Next, several leads are bent up and over the top of the PC board.
Five chip capacitors and a terminating resistor are soldered to the ground plane and a 5-tap ferrite
inductor is positioned above. Note that nearly two dozen solder joints are required to electrically connect
the various components. Finally, the entire assembly is placed into an oversized plastic tub and filled
with a potting material.
INTERNAL VIEWS
Figure 1
By comparison, the silicon delay line consists of a laser-optimized die bonded to a conventional lead
frame molded into an auto-insertable industry standard DIP or surface-mount SOIC package. The die is a
low-power CMOS design fabricated on six-inch wafers by Dallas Semiconductor’s Class 1 facility. Using
lasers for late definition of finished wafers provides both economy and maximum flexibility; both rising
and falling edges can be programmed to standard or custom delays over a wide range of values. A post-
laser final passivation step protects against contamination by covering the laser fuse windows before
packaging.
The basic building block of a silicon delay line consists of a ramp generator with associated logic (Figure
2). The input signal triggers a ramp generator that supplies a laser-adjusted voltage-to-time relationship
(Figures 3 and 4). A comparator is used to detect the ramp reaching the reference voltage (V
REF
); this sets
or resets the output latch. The DS1013 family has three independent blocks in parallel while the DS1000,
DS1005, and DS1010 families have the blocks connected in series with a single external input (Figure 5).
All silicon delay lines, unlike most TTL-based hybrids, have true CMOS output levels.
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APPLICATION NOTE 14
BASIC BUILDING BLOCK
Figure 2
J
K
INPUT
RAMP
Q
OUTPUT
LOGIC
VOLTAGE TO TIME CONVERSION
Figure 3
VOLTAGE ON
CAPACITORS
V
REF
TIME
VOLTAGE OUT
OF CMPARATOR
DELAY
TIME
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APPLICATION NOTE 14
EXPANDED BASIC BLOCK
Figure 4
DELAY LINE FAMILIES
Figure 5
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APPLICATION NOTE 14
The linear ramp generator is implemented with constant current sources charging capacitors (Figure 6).
By using a combination of several large current sources and capacitors and binary weighted smaller
current sources and capacitors, maximum flexibility with subnanosecond adjustment is obtained on a
single silicon die (Figure 7). Under the direction of a computer-controlled tester with 20-picosecond
resolution, the proper slope of the ramp (Figure 8) is obtained by directing a laser to remove the
unnecessary current sources and capacitors. This is accomplished by opening polysilicon fuses (Figure
9).
BASIC RAMP GENERATOR
Figure 6
LASER PROGRAMMABLE ELEMENTS
Figure 7
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APPLICATION NOTE 14
RANGE OF ADJUSTMENT
Figure 8
LASER BLOWING POLYSILICON FUSE
Figure 9
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