APP107.PDF

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Application Note 107
DS1020/DS1021 8-Bit
Programmable Delay Lines
www.dalsemi.com
INTRODUCTION
This application note is designed to assist in the use of the DS1020/DS1021 programmable delay lines.
The basic principles of device operation are covered in simplified form, but with sufficient detail to
enable the user to understand what is happening within the device and how this affects its use in practical
applications.
These flexible devices can be configured as traditional delay lines, as pulse width modulators or even as
programmable oscillators. A variety of configurations are illustrated, the various features of which cover
most applications.
Some of the key considerations which must be taken into account when designing in these products,
based on the experience of previous users of the devices, are also covered.
The DS1020/DS1021 are similar devices, differing only in package and step size availability and
response to power-up conditions.
KEY PRODUCT FEATURES
Programmable over 256 steps in increments of 0.15 to 2 ns (DS1020), 0.25 or 0.5 ns (DS1021)
Guaranteed monotonicity
Serial (3-wire) or parallel (8-bit) programmability
Cascadable
DIP (DS1020 only) or SOIC packaging
PRODUCT SELECTION
(all times in ns)
STEP 0 DELAY
DELAY PER STEP
10
0.15
10
10
10
10
0.25
0.5
1
2
PART NUMBER
DS1020-015
DS1020-025
DS1021-025
DS1020-050
DS1021-050
DS1020-100
DS1020-200
MAXIMUM DELAY
48.25
73.75
137.50
265.00
520.00
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110899
APPLICATION NOTE 107
CIRCUIT CONFIGURATIONS
Programmable Delay Line
Programmable Pulse Width
TIMING WAVEFORMS
Figure 1
OUTPUT WAVEFORMS
Figure 2
This is the “normal” mode of operation for the DS1020/DS1021. Input pulses applied to the device
reappear at the output after a delay time set by the device programming. Both leading and trailing edges
of the input waveform are delayed by the same amount.
The delay time can be programmed either by means of a serial data input or can be loaded into an 8-bit
parallel port. A Mode Select pin (S) determines which mode of operation is to be used. An Enable pin is
available to latch in the serial data once it has been loaded, or to load parallel data and isolate the device
from further changes to a shared parallel bus.
NOTE:
In some of the following applications control and/or data input pins have been omitted for clarity.
Unless reference is made to specific inputs, the same configuration can be used in either the serial or
parallel mode.
The DS1020/DS1021 can be combined with some simple external logic to produce a programmable pulse
width. In the example shown above the output pulse is triggered by the rising edge of the input waveform
and can be adjusted in duration from 10 ns (the latent delay of the DS1020/DS1021) up to the maximum
programmed delay value.
For correct operation over the full range of desired output pulse widths, the duration of both the high and
low states of the input must be greater than the delay time of the DS1020/DS1021 which corresponds to
the maximum output pulse width.
The rising edge of the output will be delayed with respect to the input by the propagation delay through
the two gates. The falling edge will be dependent on the programmed delay of the DS1020/DS1021 and
the propagation delay of the output gate (see diagram next page).
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APPLICATION NOTE 107
Therefore the output pulse width is given by:
t
W
= (input to falling edge of output) - (input to rising
edge of output)
= (t
DELAY
+ t
PHL
) - (t
PHL
+ t
PLH
)
= t
DELAY
- t
PLH
PULSE WIDTH MODULATOR
Figure 3
Figure 3 shows the range of pulse widths available for the various members of the DS1020/DS1021
family.
NOTE:
Using HCMOS gates the minimum pulse width will be approximately 5 ns.
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APPLICATION NOTE 107
Programmable Oscillator
If the output of the DS1020/DS1021 is inverted
and fed back to the input, a free-running
oscillator is produced. The oscillator can be
gated if desired by replacing the inverter with a
NAND or NOR function and using the
additional input as an enable.
The period of the output signal will equal
approximately twice the sum of the programmed
delay and the propagation delay through the
inverter, or more accurately:
f
O
= 1/ {2(t
DELAY
)
DS1020
+ (t
PLH
+ t
PHL
)INV}
The minimum frequency is determined by the maximum achievable delay from the DS1020/DS1021, the
maximum is determined by the propagation delay of the inverter and the step 0 delay time of the
DS1020/DS1021.
The following table summarizes some bench measurements on three of the available speed options:
DEVICE
STEP SIZE
STEP NUMBER
255
128
0
255
128
0
255
128
0
FREQUENCY
5.8
9.7
33.0
1.8
3.2
33.0
0.9
1.7
30.0
JITTER (ns)
5.0
2.0
1.0
10.0
5.0
1.5
22.0
14.0
1.5
DS1020-025
0.25 ns
DS1020-100
1 ns
DS1020-200
2 ns
In practice the speeds tend to be higher than suggested by the data sheet values for the inverter
propagation delays because the devices are more lightly loaded.
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APPLICATION NOTE 107
The maximum frequency can be increased by using a faster inverter:
DEVICE: DS1020-025
STEP
NUMBER
255
128
0
‘HC04
FREQUENCY
(MHz)
5.8
9.7
33.0
JITTER
(ns)
5.0
2.0
1.0
STEP SIZE: 0.25 ns
‘F04
FREQUENCY
JITTER
(MHz)
(ns)
6.5
2.5
10.8
1.2
47.0
0.3
The jitter values shown in these charts are approximate values for the peak to peak jitter on the output
signal. The effect of jitter increases as the operating frequency is increased, but can be minimized by
device decoupling.
The increased jitter of the oscillator using an HCMOS inverter versus an F-TTL inverter can be attributed
to the difference in noise coupled to the supply when the inverter output changes state. The HCMOS
“through current” results in a larger glitch on the supply than the bipolar totem-pole output stage.
Using this bench data we can project the performance for each member of the family across its entire
programming range. Figures 4 and 5 show the theoretical frequencies obtainable for given programmed
delay values. The first chart assumes an HCMOS type inverter or gate, the second achieves a greater
maximum frequency by using an F-TTL device.
To derive these charts the following values have been used for the propagation delays of the inverters:
‘HC04: t
PLH
= t
PHL
= 6 ns
‘F04: t
PLH
= t
PHL
= 3 ns
FREQUENCY VS. PROGRAMMED STEP (HCMOS INVERTER)
Figure 4
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