APP319.PDF

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Application Note 319
DS2152, DS2154 PCM Interface,
Interfacing to the MC68MH360 QUICC32
Interconnections between the DS2152 or DS2154 and the Motorola MC68MH360 (QUICC32) are shown
in Figure 1. The MC68MH360 can be configured as an HDLC controller implementing protocols such as
LAPD for both DS0 channel and the E1 Sa bits. The DS2152 has a built in
FULL HDLC
controller for
the FDL. Any combination of the QUICC32’s SCCs and SMCs can be processed through an internal time
slot assignor onto one or two Time Division Multiplex channels, TDMA and TDMB. In the configuration
shown, TDM channel A is used for timeslots 0–23 (T1) or 0–31 (E1) and TDM channel B is used
optionally for the Sa bit (E1). See the MC68MH360 Quad Integrated Communications Controller user’s
manual for complete details.
DS2152, DS2154 – QUICC32 INTERCONNECTIONS Figure 1
L1TXDA
L1TXDB
DS2152, DS2154 NOTES:
1.
2.
Other signals affecting operation of device are not shown.
Example circuit has RSYNC in output mode.
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APPLICATION NOTE 319
MC68360 NOTES:
1.
2.
Other signals affecting operation of device are not shown.
Use SI mode register to:
A.
Set up transmit and receive frame sync delays (0–3 clocks) to mask the F–Bit in T1
applications.
B.
Set clock edges for transmit on rising edge and receive on falling edge. CEA = CEB = 0.
C.
In the above example, TDM channel A has a common transmit/ receive clock and sync.
CTRA = 1. Use the TIMESLOT ASSIGNER to ignore Timeslot 0 for the DS2154.
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