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19-1419; Rev 4; 9/99
MAX3675/MAX3676 Evaluation Kits
General Description
The MAX3675/MAX3676 evaluation kits (EV kits) simplify
evaluation of the MAX3675/MAX3676 622Mbps clock-
recovery and data-retiming IC with limiting amplifier.
The EV kits enable testing of all MAX3675/MAX3676
functions. They provide selectable analog or digital
data inputs, as well as differential PECL-compatible
data and clock outputs.
The differential data and clock outputs have 50Ω atten-
uators on-board to allow direct connection to a high-
speed oscilloscope.
The MAX3675/MAX3676 EV kits come configured for
+3.3V operation and consume approximately 120mA.
____________________________Features
o
SMA Connections for all Data and Clock I/Os
o
Test Points for Monitoring
Received-Signal-Strength Indicator (RSSI)
Loss-of-Power (LOP)
Loss-of-Lock (LOL)
LOP Threshold Level (V
TH
)
o
+3.3V Single-Supply Operation
o
Fully Assembled and Tested
Evaluate: MAX3675/MAX3676
Ordering Information
PART
MAX3675EHJEVKIT
MAX3676EHJEVKIT
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
IC PACKAGE
5mm 32 TQFP
5mm 32 TQFP
Component Suppliers
SUPPLIER
Coilcraft
PHONE
847-639-6400
FAX
847-639-1469
__________________________________________________________________Component List
DESIGNATION
C1–C4, C7–C10, C13,
C21, C23, C25, C27
C5, C6, C14
C12
C22, C24, C26,
C28, C29, C30
C20
C11, C16
C15
C17
C19
L1, L2
QTY
13
3
1
6
1
0
1
1
1
0
DESCRIPTION
0.1µF, 25V ceramic capacitors
0.01µF, 25V ceramic capacitors
2.2µF ±20% X7R ceramic cap
or 16V (min) tantalum capacitor
100pF, 25V ceramic capacitors
2.2µF, 25V ceramic capacitor
Open
0.047µF, 25V ceramic capacitor
0.033µF, 25V ceramic capacitor
33µF ±20% capacitor
Not included. Use a 56nH induc-
tor for additional power-supply
decoupling, if needed.
56nH inductors
Coilcraft 0805HS-560TKBC
130Ω ±1% resistors
82.5Ω ±1% resistors
49.9Ω ±1% resistors
24.3Ω ±1% resistors
27.4Ω ±1% resistors
DESIGNATION
R10, R14, R18, R22
R23
R23
R24
R25
R26
R27
R28, R32, R33
R29
R31
R30
DDI+, DDI-, ADI+,
ADI-, SDO+, SDO-,
SCLKO+, SCLKO-
V
CC
, JP1, JP2, GND
JP4, JP5, JP6,
JP7, JP9
JP8, JP10
TP1–TP4
None
U1
None
QTY
4
1
1
1
1
1
1
3
1
1
1
8
4
5
2
6
3
1
1
DESCRIPTION
221Ω ±1% resistors
52.3Ω ±1% resistor (MAX3675EHJ)
0Ω resistor (MAX3676EHJ)
3kΩ ±5% resistor
3.3kΩ ±5% resistor
10kΩ potentiometer
20kΩ ±5% resistor
10kΩ ±5% resistors
120kΩ ±5% resistor
100kΩ potentiometer
0Ω resistor
SMA connectors
2-pin headers
Not Installed
3-pin headers
1-pin headers
Shunts for JP2, JP8, and JP10
MAX3675EHJ or MAX3676EHJ
MAX3675 or MAX3676 data sheet
L3, L4
R2, R4, R9, R13,
R17, R21
R1, R3
R5, R6
R7, R11, R15, R19
R8, R12, R16, R20
2
6
2
2
4
4
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX3675/MAX3676 Evaluation Kits
Evaluate: MAX3675/MAX3676
_______________Detailed Description
The MAX3675/MAX3676 EV kits are fully assembled
and factory tested. They enable testing of all MAX3675/
MAX3676 functions.
SDO+
RF
&
DC
V
CC
-2V
DC
50Ω
BIAS-T
RF
Test Equipment Required
•
•
•
•
+3.3V power supply with 200mA current capability
Signal-source, 622Mbps BER test set
Jitter analyzer capable of 622Mbps performance
Oscilloscope with at least 1GHz performance
MAX3675EHJ
MAX3676EHJ
EVKITS
SDO-
OUTPUT
ATTENUATORS
REMOVED
ON SDO+
AND SCLKO+
SCLKO+
50Ω
BERT
V
CC
-2V
DC
50Ω
BIAS-T RF
CLOCK
IN
DATA
IN
ERROR DETECTOR
Connections
The digital inputs (DDI+, DDI-) have on-board AC-cou-
pling capacitors followed by Thevenin-equivalent 50Ω
terminations. The analog inputs (ADI+, ADI-) are
equipped with DC 50Ω loads followed by AC-coupling
capacitors. Remember that the analog inputs to the
MAX3675/MAX3676 must be AC-coupled. All of the
MAX3675/MAX3676 data and clock outputs (SDO+,
SDO-, SCLKO+, SCLKO-) are terminated on-board with
50Ω, PECL, 2X attenuators. Configured in this way,
these outputs can be directly connected to the 50Ω
inputs of a high-speed oscilloscope for analysis.
RF
&
DC
SCLKO-
50Ω
Figure 1. ECL Interface to Test Equipment
Setup
1) Select either the PECL (DDI ENABLE) or the analog
(ADI ENABLE) inputs with jumper JP10.
2) Verify that the shunt across jumper JP2 is in place.
3) Verify that the shunt is across pins 2 and 3 of jumper
JP8.
4) Verify that resistor R23 is 52.3Ω (MAX3675) or
0Ω (MAX3676).
5) Connect the +3.3V power supply to the appropriate
terminals marked on the EV kit and apply power.
6) Connect a 622Mbps PRBS NRZ signal to the select-
ed inputs with 50Ω cables.
7) Connect the outputs to a 50Ω high-speed oscillo-
scope.
Jitter analysis and product performance can also be
observed by appropriately interfacing the EV kit with a
bit-error-rate tester (BERT) and a jitter analyzer.
1) Remove the data and clock output attenuators for
those signal lines you intend to observe. For exam-
ple, if you intend to observe SDO+, then open R9
and R10, and short R7 and R8.
2) Use a 50Ω bias tee to bias the MAX3675/MAX3676
outputs.
Adjustments, Jumpers, and Test Points
Two adjustments are available on the MAX3675/ MAX3676
EV kits: VTH ADJ (R31) and PHADJ (R26). VTH ADJ is
used to set the loss-of-power threshold level for the LOP
monitor. PHADJ, although not required, can be used to
shift the sampling edge of the recovered clock relative
to the center of the data eye. Be sure to remove jumper
JP2 if you intend to adjust PHADJ. See Table 1 for
jumper functions.
The following high-impedance test points are provided
for signal monitoring:
• RSSI, used to monitor the received-signal-strength
indicator output
• LOP, used to monitor loss of power
•
LOL,
used to monitor loss of lock
• V
TH
, used to monitor the threshold voltage level
Interfacing with ECL Test Equipment
Not all jitter analyzers and BERTs can easily interface
with the EV kits’ PECL output signal levels. If your test
equipment requires standard ECL levels, then bias tees
are required (Figure 1). For example, if using an HP
BERT, you must do the following:
2
_______________________________________________________________________________________
MAX3675/MAX3676 Evaluation Kits
Table 1. Jumper Functions
NAME
JP1
JP2
TYPE
2-Pin
2-Pin
DESCRIPTION
Disables the MAX3675/
MAX3676 loop filter
Disables the phase
adjustment (R26)
NORMAL
POSITION
Open (enabled)
Shorted
(disabled)
Layout Considerations
MAX3675/MAX3676 performance can be greatly affect-
ed by circuit board layout and design. Use good high-
frequency design techniques, including minimizing
ground inductances and using fixed-impedance trans-
mission lines on the data and clock signals.
Evaluate: MAX3675/MAX3676
Not supplied. The PC
JP4, JP5,
board trace between
2-Pin
JP6, JP7
jumper pads can be cut
open if analysis requires
JP8
3-Pin
Disables VTH
adjustment (R31)
Shorted
Pins 2 and 3
shorted (enabled)
JP10
Used to select between
the digital inputs (DDI
3-Pin ENABLE) and the analog
inputs (ADI ENABLE) of
the MAX3675/MAX3676
—
_______________________________________________________________________________________
3
Evaluate: MAX3675/MAX3676
+3.3V
R7
24.3Ω
SDO+
LOL
R25
3.3k
C14
0.01µF
+3.3V
R11
24.3Ω
SDO-
R28
10k
R13
130Ω
VCCVCO
VCCPLL
24
22
23
21
20
19
18
17
JP9
R15
24.3Ω
R16
27.4Ω
+3.3V
SCLK+
C8
0.1µF
R14
221Ω
R12
27.4Ω
C7
0.1µF
R10
221Ω
R9
130Ω
R8
27.4Ω
3
1
C11
OPEN
2
C12
R23
NOTE 1 2.2µF
R27
20k
C13
0.1µF
1
2
3
OLC+
OLC-
RSSI
GND
INV
VTH
LOP
GND
JP10
1
2
3
4
5
6
7
8
GND
LOP
C5
R5
0.01µF
49.9Ω
C17
0.033µF
R32
10k
C16
OPEN
V
TH
R33
10k
1
R30
0Ω
2
MAX3675/MAX3676 Evaluation Kits
Figure 2. MAX3675/MAX3676EHJ EV Kits Schematic
JP1
FILTER
DISABLE
R24
3k
JP2
PHASE R26
ADJ 10k
PHASE
ADJ
DISABLE
R2
130Ω
VCCOUT
+3.3V
VCCOUT
R19
24.3Ω
R20
27.4Ω
SCLK-
R17
130Ω
C9
0.1µF
GND
FIL+
FIL-
V
CC
PHADJ+
PHADJ-
V
CC
LOL
R18
221Ω
+3.3V
ADI
ENABLE
VCCOUT
R21
130Ω
+3.3V
R4
130Ω
DDI
ENABLE
C15
0.047µF
25
26
27
28
29
30
VCCPA 31
32
GND
GND
V
CC
DDI+
SDO+
DDI-
MAX3675EHJ
SDO-
INSEL
MAX3676EHJ
V
CC
ADI-
SCLKO+
ADI+
SCLKO-
V
CC
V
CC
CFILT
C10
0.1µF
16
15
14
13
12
11
10
9
R22
221Ω
JP4
L1
SHORT
VCCVCO
3
VTH ADJ
R31
100k
C21
0.1µF
JP5
L2
SHORT
C22
100pF
VCCPLL
C24
100pF
+3.3V
C19
33µF
GND
C27
0.1µF
C28
100pF
C29
100pF
C30
100pF
C20
2.2µF
JP6
VCCPA
C25
L4 0.1µF
56nH
JP7
C26
100pF
VCCOUT
C23
L3 0.1µF
56nH
C6
R6
49.9Ω 0.01µF
R29
120k
RSSI
3
1
JP8 2
V
TH
TEST
4
+3.3V
C3
0.1µF
DDI+
C1
0.1µF
R1
82.5Ω
C4
0.1µF
DDI-
C2
0.1µF
R3
82.5Ω
ADI-
_______________________________________________________________________________________
ADI+
NOTE 1:
R23 = 52.3Ω (MAX3675)
R23 = 0Ω (MAX3676)
MAX3675/MAX3676 Evaluation Kits
Evaluate: MAX3675/MAX3676
1.0"
1.0"
Figure 3. MAX3675/MAX3676 EV Kits Component Placement
Guide
Figure 4. MAX3675/MAX3676 EV Kits PC Board Layout—
Component Side
1.0"
1.0"
Figure 5. MAX3675/MAX3676 EV Kits PC Board Layout—
Ground Plane
Figure 6. MAX3675/MAX3676 EV Kits PC Board Layout—
Power Plane
5
_______________________________________________________________________________________

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