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19-1207; Rev 0; 3/97
KIT
ATION
EVALU
BLE
AVAILA
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
_______________General Description
The MAX3691 serializer is ideal for converting 4-bit-
wide, 155Mbps parallel data to 622Mbps serial data in
ATM and SDH/SONET applications. Operating from a
single +3.3V supply, this device accepts low-voltage
differential-signal (LVDS) clock and data inputs for
interfacing with high-speed digital circuitry, and deliv-
ers a 3.3V PECL serial-data output. A fully integrated
PLL synthesizes an internal 622Mbps serial clock from
a 155.52MHz reference clock.
The MAX3691 is available in the extended-industrial
temperature range (-40°C to +85°C), in a 32-pin TQFP
package.
____________________________Features
o
Single +3.3V Supply
o
155Mbps Parallel to 622Mbps Serial Conversion
o
215mW Power
o
LVDS Parallel Clock and Data Inputs
o
Differential 3.3V PECL Serial-Data Output
MAX3691
________________________Applications
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects
______________Ordering Information
PART
MAX3691ECJ
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
32 TQFP
Pin Configuration appears at end of data sheet.
___________________________________________________Typical Operating Circuit
0.1µF
LVDS CRYSTAL REFERENCE
0.1µF
V
CC
= +3.3V
PCLKI- PCLKI+ RCLK- RCLK+
PD0+
PD0-
OVERHEAD
GENERATION
PD1+
PD1-
PD2+
PD2-
PD3+
PD3-
PCLKO- PCLKO+
SD- SD+
V
CC
= +3.3V
130Ω
130Ω
1.5k
24.9k
100pF
FIL-
V
CC
= +3.3V
V
CC
GND
FIL+
MAX3691
MAX3667
82Ω
82Ω
THIS SYMBOL REPRESENTS A TRANSMISSION LINE
OF CHARACTERISTIC IMPEDANCE (Z
0
= 50Ω)
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
MAX3691
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
V
CC
.........................................................................-0.5V to 5V
All Inputs.................................................-0.5V to (V
CC
+ 0.5V)
Output Current
LVDS Outputs (PCLKO±)................................................10mA
PECL Outputs (SD±).......................................................50mA
Continuous Power Dissipation (T
A
= +85°C)
TQFP (derate 10.20mW/°C above +85°C) ...................663mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, differential LVDS loads = 100Ω ±1%, PECL loads = 50Ω ±1% to (V
CC
- 2V), T
A
= -40°C to +85°C, unless
otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C.)
PARAMETER
Supply Current
PECL OUTPUTS (SD±)
Output High Voltage
Output Low Voltage
V
OH
V
OL
T
A
= +25°C to +85°C
T
A
= -40°C
T
A
= +25°C to +85°C
T
A
= -40°C
Differential input voltage =
100mV
Common-mode voltage =
50mV
V
CC
- 1.03
V
CC
- 1.08
V
CC
- 1.81
V
CC
- 1.95
V
CC
- 0.88
V
CC
- 0.88
V
CC
- 1.62
V
CC
- 1.62
V
V
SYMBOL
I
CC
CONDITIONS
PECL outputs unterminated
MIN
38
TYP
65
MAX
100
UNITS
mA
LVDS INPUTS AND OUTPUTS (PCLKI±, RCLK±, PCLKO±, PD_±)
Input Voltage Range
Differential Input Threshold
Threshold Hysteresis
Differential Input Resistance
Output High Voltage
Output Low Voltage
Differential Output Voltage
Change in Magnitude of Differential Output
Voltage for Complementary States
Output Offset Voltage
Change in Magnitude of Output Offset Voltage
for Complementary States
Single-Ended Output Resistance
Change in Magnitude of Single-Ended Output
Resistance for Complementary States
V
I
V
IDTH
V
HYST
R
IN
V
OH
V
OL
V
OD
∆V
OD
V
OS
∆V
OS
R
O
∆R
O
40
70
±1
T
A
= +25°C
1.125
0.925
250
400
25
1.275
25
140
±10
85
0
-100
70
100
115
1.475
2.4
100
V
mV
mV
Ω
V
V
mV
mV
V
mV
Ω
%
2
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, differential LVDS load = 100Ω ±1%, PECL loads = 50Ω ±1% to (V
CC
- 2V) T
A
= +25°C, unless otherwise
noted. Typical values are at V
CC
= +3.3V.) (Note 1)
PARAMETER
Serial Clock Rate
Parallel Data-Setup Time
Parallel Data-Hold Time
PCLKO to PCLKI Skew
Output Jitter
PECL Differential Output
Rise/Fall Time
SYMBOL
f
SCLK
t
SU
t
H
t
SKEW
Φ
0
t
R,
t
F
T
A
= -40°C to +85°C (Note 2)
400
200
600
-0.7
+3.3
13
CONDITIONS
MIN
TYP
622.08
MAX
UNITS
MHz
ps
ps
ns
ps
RMS
ps
MAX3691
Note 1:
AC characteristics guaranteed by design and characterization.
Note 2:
Assumes a 50% duty cycle ±5%.
__________________________________________Typical Operating Characteristics
(V
CC
= +3.0V to +3.6V, differential LVDS loads = 100Ω, unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
MAX3691-01
PARALLEL DATA-SETUP TIME
vs. TEMPERATURE
MAX3691-02
PARALLEL DATA-HOLD TIME
vs. TEMPERATURE
MAX3691-03
100
-20
PARALLEL DATA-SETUP TIME (ps)
250
PARALLEL DATA-HOLD TIME (ps)
80
SUPPLY CURRENT (mA)
-40
230
60
-60
210
40
-80
190
20
-100
170
0
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
-120
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
150
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
_______________________________________________________________________________________
3
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
MAX3691
____________________________Typical Operating Characteristics (continued)
(V
CC
= +3.0V to +3.6V, differential LVDS loads = 100Ω, unless otherwise noted.)
PCLKO-to-PCLKI SKEW
vs. TEMPERATURE
MAX3691-04
SERIAL-DATA OUTPUT EYE DIAGRAM
(622Mbps, 2
7
-1 PRBS)
MAX3691-05
SERIAL-DATA OUTPUT JITTER
MAX3691-06
6
1.21V
908mV
PCLKO-TO-PCLKI SKEW (ns)
4
OC-12
SONET MASK
2
62mV/
div
10mV/
div
f
RCLK
= 155.52MHz
0
-2
0.59V
-50
-25
0
25
50
75
100
161ps/div
Mean 23.88ns
RMS∆ 8.418ps
PkPk 70.2ps
TEMPERATURE (°C)
808mV
10ps/div
µ±1σ
68.774%
µ±2σ
95.534%
µ±3σ
99.738%
-4
______________________________________________________________Pin Description
PIN
1, 3, 5, 7
2, 4, 6, 8
9, 17, 18,
19, 24,
25, 32
10
11
12, 13, 16,
20, 21,
28, 29
14
15
22
23
26
27
30
31
4
NAME
PD0+ to PD3+
PD0- to PD3-
GND
PCLKO-
PCLKO+
V
CC
SD-
SD+
FIL-
FIL+
RCLK+
RCLK-
PCLKI+
PCLKI-
FUNCTION
Noninverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
Inverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
Ground
Inverting LVDS Parallel-Clock Output. Use PCLKO to clock the overhead management circuit.
Noninverting LVDS Parallel-Clock Output. Use PCLKO to clock the overhead management circuit.
+3.3V Supply Voltage
Inverting PECL Serial-Data Output
Noninverting PECL Serial-Data Output
Filter Capacitor Input. See
Typical Operating Circuit
for external-component connections.
Filter Capacitor Input. See
Typical Operating Circuit
for external-component connections.
Noninverting LVDS Reference Clock Input. Connect (AC couple) a crystal reference clock
(155.52MHz) to the RCLK inputs.
Inverting LVDS Reference Clock Input. Connect (AC couple) a crystal reference clock (155.52MHz)
to the RCLK inputs.
Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the
PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal.
Inverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI
inputs. Note that data is updated on the positive transition of the PCLKI signal.
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
_______________Detailed Description
The MAX3691 serializer comprises a 4-bit parallel input
register, a 4-bit shift register, control and timing logic, a
PECL output buffer, LVDS input/output buffers, and a
frequency-synthesizing PLL (consisting of a phase/
frequency detector, loop filter/amplifier, and voltage-
controlled oscillator). This device converts 4-bit-wide,
155Mbps data to 622Mbps serial data (Figure 1).
The PLL synthesizes an internal 622Mbps reference
used to clock the output shift register. This clock is
generated by locking onto the external 155.52MHz
reference-clock signal (RCLK).
MAX3691
The incoming parallel data is clocked into the
MAX3691 on the rising transition of the parallel-clock-
input signal (PCLKI). The control and timing logic
ensure proper operation if the parallel-input register is
latched within a window of time that is defined with
respect to the parallel-clock-output signal (PCLKO).
PCLKO is the synthesized 622Mbps internal serial-
clock signal divided by four. The allowable PCLKO-to-
PCLKI skew is -0.7ns to +3.3ns. This defines a timing
window at about the PCLKO rising edge, during which
a PCLKI rising edge may occur. Figure 2 is the timing
diagram.
PD3+
PD3-
LVDS
MAX3691
4-BIT
PARALLEL
INPUT
REGISTER
PD2+
PD2-
LVDS
PD1+
PD1-
LVDS
PD0+
PD0-
LVDS
PCLKI+
LVDS
PCLKI-
SHIFT
4-BIT
SHIFT
REGISTER
PECL
SD+
SD-
RCLK+
LVDS
RCLK-
PHASE/FREQ
DETECT
VCO
CONTROL
LATCH
LVDS
FIL+ FIL-
PCLKO+ PCLKO-
Figure 1. Functional Diagram
_______________________________________________________________________________________
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