mega103_progspec.pdf

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ATmega603/103 serial programming
Insertion to section “Memory
programming“
Add the following text and table to the end of section “Pro-
gramming the Flash and EEPROM”:
During programming, the supply voltage must be in accor-
dance with Table 1.
Table 1.
Supply voltage during programming
Part
ATmega103/603
ATmega103L/603L
Serial
programming
4.0 - 5.0 Volt
3.2 - 3.6 Volt
Parallel
programming
4.0 - 5.0 Volt
3.2 - 5.0 Volt
Correction to “Parallel programming”
Point 4. under
Chip Erase:
Change:
Give XTAL 1 a .... , then wait for at least 10ms. ....
to
Give XTAL 1 a ....., then wait for at least the prescribed
time
t
WD_FLASH
from Table 2 in section Serial Downloading.
...
1
Serial Downloading
Both the Flash and EEPROM memory arrays can be pro-
grammed using the serial interface while RESET is pulled
to GND, or when PEN is low during Power On Reset. The
serial interface consists of pins SCK, RXD/PDI (input) and
TXD/PDO (output). After RESET is set low, the Program-
ming Enable instruction needs to be executed first before
program/erase operations can be executed.
When programming the EEPROM, an auto-erase cycle is
built into the self-timed programming operation (in the
serial mode ONLY) and there is no need to first execute the
Chip Erase instruction. The Chip Erase operation turns the
content of every memory location in both the Program and
EEPROM arrays into $FF.
The Program and EEPROM memory arrays have separate
address spaces:
ATmega603: $0000 to $7FFF for program memory and
$0000 to $07FF for EEPROM memory.
ATmega103: $0000 to $FFFF for program memory and
$0000 to $0FFF for EEPROM memory.
Either an external system clock is supplied at pin XTAL1 or
a crystal needs to be connected across pins XTAL1 and
XTAL2.The minimum low and high periods for the serial
clock (SCK) input are defined as follows:
Low: > 2 XTAL1 clock cycles
High: > 2 XTAL1 clock cycles
Data Polling for the EEPROM
When a new EEPROM byte has been written and is being
programmed into the EEPROM, reading the address loca-
tion being programmed will give the value P1 (please refer
to Table 3.) until the auto-erase is finished, and then the
value P2.
At the time the device is ready for a new EEPROM byte,
the programmed value will read correctly. This is used to
determine when the next byte can be written. This will not
work for the values P1 and P2, so when programming
these values, the user will have to wait for at least the pre-
scribed time
t
WD_EEPROM
(please refer to Table 2) before pro-
gramming the next byte. As a chip-erased device contains
$FF in all locations, programming of addresses that are
meant to contain $FF, can be skipped. This does not apply
if the EEPROM is reprogrammed without chip erasing the
device.
Data polling is
not
implemented for the Flash!
SERIAL PROGRAMMING ALGORITHM
To program and verify the ATmega103/L in the serial pro-
gramming mode, the following sequence is recommended
(See 4-byte instruction formats in Table 39.):
1. Power-up sequence: Apply power between V
CC
and
GND while RESET and SCK are set to '0'. The
RESET signal must be kept low during the complete
serial programming session. If a crystal is not con-
nected across pins XTAL1 and XTAL2, apply a clock
signal to the XTAL1 pin. In some systems, the pro-
grammer can not guarantee that SCK is held low
during power-up. In this case, RESET must be
given a positive pulse of at least two XTAL1 cycles
duration after SCK has been set to '0'.
As an alternative to using the RESET signal, PEN can
be held low during Power On Reset while SCK is set to
'0'. In this case, only the PEN value at Power On Reset
is important. If a crystal is not connected across pins
XTAL1 and XTAL2, apply a clock signal to the XTAL1
pin. If the programmer cannot guarantee that SCK is
held low during power-up, the PEN method cannot be
used.The device must be powered down in order to
commence normal operation when using this method.
2. Wait for at least 20 ms and enable serial program-
ming by sending the Programming Enable serial
instruction to pin PE0(PDI/RXD).
3. When issuing the third byte in Programming Enable,
the value sent as byte number two ($53), will echo
back during transmission of byte number three. All
four bytes in programming enable must be transmit-
ted. If the $53 did not echo back, give SCK a posi-
tive pulse and issue a new Programming Enable
command. If the $53 is not seen within 32 attempts,
there is no functional device connected.
4. If a chip erase is performed (must be done to erase
the Flash), wait at least (2 x t
WD_FLASH
), give RESET
a positive pulse of at least two XTAL1 cycles dura-
tion after SCK has been set to '0', and start over
from Step 2.
5. The Flash is programmed one page at a time. The
memory page is loaded one byte at a time by sup-
plying the 7 LSB of the address and data together
with the Load Program Memory Page instruction.
The Program Memory Page is stored by loading the
Write Program Memory Page instruction with the 9
MSB of the address. The next page can be written
after t
WD_FLASH
, i.e., writing 256 bytes takes
t
WD_FLASH
. Accessing the serial programming inter-
face before the Flash write operation completes can
result in incorrect programming.
6. The EEPROM array is programmed one byte at a
time by supplying the address and data together
with the appropriate Write instruction. An EEPROM
memory location is first automatically erased before
new data is written. If polling is not used, the user
must wait at least t
WD_EEPROM
before issuing the next
byte. (Please refer to Table 2)
2
ATmega103/603 serial programming
ATmega603/103 serial programming
7. Any memory location can be verified by using the
Read instruction which returns the content at the
selected address at serial output PE1(PDO/TXD).
8. At the end of the programming session, RESET can
be set high to commence normal operation.
9. Power-off sequence (if needed): Set XTAL1 to ‘0’ (if
a crystal is not used). Set RESET to ‘1’. Turn V
CC
power off
Symbol
t
WD_FLASH
t
WD_EEPROM
3.2V
56ms
9ms
3.6V
43ms
7ms
Table 2 shows the actual delays used in this section.
Please NOTE: The MISO pin is not Hi-Z during serial pro-
gramming.
Table 2.
Minimum wait delay before writing the next Flash or EEPROM location
4.0V
35ms
6ms
5.0V
22ms
4ms
Table 3.
Read back value during EEPROM polling
Revision
F
G
P1
$7F
$80
P2
$7F
$7F
3

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