Code lock.TXT

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design:   C:\Program Files\Labcenter Electronics\Proteus 7 Professional\SAMPLES\Code lock.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  03/09/08
Modified: 03/10/08

*PROPERTIES,0    

*MODELDEFS,0    

*PARTLIST,12   
BUZ1,BUZZER,BUZZER,BUFFERTIME=200ms,EID=19,FREQ=500Hz,LOAD=12,PINSWAP="1,2",SAMPLERATE=44100,VNOM=12V
C1,POLYSTYRENE4N7,22p,CODE="Maplin RG54J",EID=15,PACKAGE=AXIAL80,PINSWAP="1,2"
C2,POLYSTYRENE4N7,22p,CODE="Maplin RG54J",EID=16,PACKAGE=AXIAL80,PINSWAP="1,2"
D1,1N4007,1N4007,EID=11,PACKAGE=DO41
D2,LED-RED,LED-RED,BV=4V,EID=18,IMAX=10mA,ROFF=100k,RS=3,TLITMIN=0.1ms,VF=12V
Q1,BC547,BC547,EID=12,PACKAGE=TO92/18
R1,MINRES12K,1k,CODE=M12K,EID=13,PACKAGE=RES40,PINSWAP="1,2",PRIMTYPE=RESISTOR
R2,MINRES12K,12k,CODE=M12K,EID=14,PACKAGE=RES40,PINSWAP="1,2",PRIMTYPE=RESISTOR
RL1,G2R-14-DC12,G2R-14-DC12,EID=F,PACKAGE=RLY-OMRON-G2R-A1,RCOIL=16.5,RCONTACT=30m,VCOIL=12V
U1,PIC16F84A,PIC16F84A,CFGWORD=0x3FFB,CLOCK=4MHz,DBG_GENERATE_CLKOUT=0,DBG_RANDOM_DMEM=0,DBG_RANDOM_PMEM=0,DBG_STARTUP_DELAY=0,DBG_WAKEUP_DELAY=0,EID=E,EPR_WRITEDATA_DELAY=10m,ITFMOD=PIC,MODDATA="64,255",MODDLL=PIC16,PACKAGE=DIL18,PORTTDHL=0,PORTTDLH=0,PROGRAM="D:\Electronica\Control touch&swich\Phase84\V0-0-0\phase84.hex",TRACE_DEFAULT=1,WDT_PERIOD=18m
V1,VSOURCE,12V,EID=17
X1,CRYSTAL,4MHZ,EID=10,FREQ=4MHz,PACKAGE=XTAL18

*NETLIST,25   
#00000,3
U1,PS,16
X1,PS,2
C1,PS,1

#00001,1
U1,IO,6

#00002,2
U1,IO,7
R2,PS,1

#00003,2
U1,IO,8
R1,PS,2

#00004,2
U1,IO,9
BUZ1,PS,1

#00005,1
U1,IO,10

#00006,1
U1,IO,11

#00007,1
U1,IO,12

#00008,1
U1,IO,13

#00009,1
U1,IO,17

#00010,1
U1,IO,18

#00011,1
U1,IO,1

#00012,1
U1,IO,2

#00013,1
U1,IO,3

#00014,3
U1,PS,15
X1,PS,1
C2,PS,1

#00015,4
U1,PS,4
V1,PS,1
RL1,PS,C1
D1,PS,K

#00018,1
RL1,PS,COM

#00019,1
RL1,PS,NO

#00020,3
RL1,PS,C2
D1,PS,A
Q1,PS,1

#00021,1
RL1,PS,NC

#00022,2
Q1,PS,2
R1,PS,1

#00023,6
Q1,PS,3
C2,PS,2
V1,PS,2
C1,PS,2
D2,PS,K
BUZ1,PS,2

#00024,2
R2,PS,2
D2,PS,A

GND,3,STRAT=POWER
VSS,PT
GND,PR
U1,PP,5

VCC/VDD,3,STRAT=POWER
VDD,PT
VCC/VDD,PR
U1,PP,14

*GATES,0