07397003.pdf

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2001-12-21
PRODUKTINFORMATION
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ELFA artikelnr
73-970-03 M24C01-WBN6 128x8 EEPROM
73-970-11 M24C01-WMN6 128x8 EEPROM
73-970-29 M24C02-WBN6 256x8 EEPROM
73-970-37 M24C02-WMN6 256x8 EEPROM
73-970-45 M24C04-WBN6 512x8 EEPROM
73-970-52 M24C04-WMN6 512x8 EEPROM
73-970-60 M24C08-WBN6 1Kx8 EEPROM
73-970-78 M24C08-WMN6 1Kx8 EEPROM
73-970-86 M24C16-WBN6 2Kx8 EEPROM
73-970-94 M24C16-WMN6 2Kx8 EEPROM
M24C16, M24C08
M24C04, M24C02, M24C01
16/8/4/2/1 Kbit Serial I²C Bus EEPROM
s
Two Wire I
2
C Serial Interface
Supports 400 kHz Protocol
SBGA
s
Single Supply Voltage:
– 4.5V to 5.5V for M24Cxx
– 2.5V to 5.5V for M24Cxx-W
– 1.8V to 5.5V for M24Cxx-R
– 1.8V to 3.6V for M24Cxx-S
8
1
PDIP8 (BN)
0.25 mm frame
SBGA5 (EA)
75 mil width
s
s
s
s
s
s
s
s
Write Control Input
BYTE and PAGE WRITE (up to 16 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Behavior
More than 1 Million Erase/Write Cycles
More than 40 Year Data Retention
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
DESCRIPTION
These I
2
C-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 2048/1024/512/256/128 x 8 bit
(M24C16, M24C08, M24C04, M24C02, M24C01),
and operate with a power supply down to 2.5 V (for
the -W version of each device), and down to 1.8 V
(for the -R and -S versions of each device).
The M24C16, M24C08, M24C04, M24C02,
M24C01 are available in Plastic Dual-in-Line,
Plastic Small Outline and Thin Shrink Small
Outline packages. The M24C16-S is also
available in a Chip Scale package.
Table 1. Signal Names
E0, E1, E2
SDA
SCL
WC
V
CC
V
SS
Chip Enable
Figure 1. Logic Diagram
VCC
3
E0-E2
SCL
WC
M24Cxx
SDA
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
VSS
AI02033
November 2001
1/21
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 2A. DIP Connections
M24Cxx
16Kb /8Kb /4Kb /2Kb /1Kb
NC / NC / NC / E0 / E0
NC / NC / E1 / E1 / E1
NC / E2 / E2 / E2 / E2
VSS
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
AI02034D
Note: 1. NC = Not Connected
Figure 2B. SO Connections
M24Cxx
16Kb /8Kb /4Kb /2Kb /1Kb
NC / NC / NC / E0 / E0
NC / NC / E1 / E1 / E1
NC / E2 / E2 / E2 / E2
VSS
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
AI02035D
Note: 1. NC = Not Connected
Figure 2C. TSSOP Connections
M24Cxx
16Kb /8Kb /4Kb /2Kb /1Kb
NC / NC / NC / E0 / E0
NC / NC / E1 / E1 / E1
NC / E2 / E2 / E2 / E2
VSS
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
AI02036D
Note: 1. NC = Not Connected
Figure 2D. SBGA Connections (top view, marking side, with balls on the underside)
M24C16
2
WC
3
SDA
1
VCC
5
SCL
4
VSS
AI02796F
2/21
M24C16, M24C08, M24C04, M24C02, M24C01
Table 2. Absolute Maximum Ratings
1
Symbol
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature
Lead Temperature during
Soldering
Input or Output range
Supply Voltage
Electrostatic Discharge Voltage (Human Body model)
3
PDIP8: 10 seconds
SO8: 20 seconds (max)
2
TSSOP8: 20 seconds (max)
2
Value
–40 to 125
–65 to 150
260
235
235
–0.6 to 6.5
–0.3 to 6.5
4000
Unit
°C
°C
°C
V
V
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. IPC/JEDEC J-STD-020A
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500
Ω,
R2=500
Ω)
These devices are compatible with the I
2
C
memory protocol. This is a two wire serial interface
that uses a bi-directional data bus and serial clock.
The devices carry a built-in 4-bit Device Type
Identifier code (1010) in accordance with the I
2
C
bus definition.
The device behaves as a slave in the I
2
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are
initiated by a Start condition, generated by the bus
master. The Start condition is followed by a Device
Select Code and RW bit (as described in Table 3),
terminated by an acknowledge bit.
When writing data to the memory, the device
inserts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V
CC
has reached the POR
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
VCC
20
Maximum RP value (kΩ)
16
RL
12
8
4
0
10
100
CBUS (pF)
AI01665
RL
SDA
MASTER
fc = 100kHz
fc = 400kHz
SCL
CBUS
CBUS
1000
3/21
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 4. I
2
C Bus Protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START
Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP
Condition
AI00792B
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V
CC
drops from the operating
voltage, below the POR threshold value, all
operations are disabled and the device will not
respond to any command. A stable and valid V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor must be
connected from Serial Clock (SCL) to V
CC
. (Figure
3 indicates how the value of the pull-up resistor
can be calculated). In most applications, though,
this method of synchronization is not employed,
and so the pull-up resistor is not necessary,
provided that the bus master has a push-pull
(rather than open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V
CC
.
(Figure 3 indicates how the value of the pull-up
resistor can be calculated).
Chip Enable (E0, E1, E2)
These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. These
inputs must be tied to V
CC
or V
SS
, to establish the
Device Select Code.
4/21

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