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A REMARKABLE ENCAPSULATION INNOVATION HERALDS EVEN SMALLER IC
PACKAGES REPORTS IAN POOLE.
There is always pressure on
electronics designers to fit in-
creasing amounts of electronics
into even smaller packages.
Any electronics designer today
will say that even though the
level of integration is increasing,
there is always a problem trying
to fit all the electronics onto a
given board, because greater
levels of functionality are
needed.
There are a number of
methods that are employed to
relieve the problem. Tracks on
the printed circuit boards can be
made thinner. Via holes passing
from one layer to another can
be made smaller, or buried
within the circuit board itself if
they connect two internal layers.
Using smaller components
can make further improve-
ments. Resistors and capaci-
tors, for example, can be re-
duced in size. Some years ago
these components had leads
that were placed through holes
in the boards. The introduction
of surface mount technology
(SMT) lead to a quantum leap in
size reduction. Now even these
components are being made yet
smaller.
Integrated circuits have also
reduced in size with the intro-
duction of surface mount tech-
nology. Dual-in-line packages
have given way to a variety of
surface mount packages. How-
ever, in just the same way that
surface mount was a major step
forwards, so further advances
need to be made if the trend of
miniaturization is to continue.
PACKAGE SIZE
One area that is being in-
vestigated is in the use of IC
packages. Here a large amount
of space is wasted, and this be-
comes particularly crucial if the
package is only used to contain
a comparatively simple func-
tion.
In many designs there are a
large number of these ICs, be-
cause it is not possible to place
all the circuitry onto one chip.
This can result from the fact
that a proprietary chip is used
and, by its very nature, it will be
general and not all the functions
for the specific application will
be included.
Alternatively, when ASICs
or other application-specific
chips are used it may not be
possible to include everything,
because the number of pins on
the package is limited. In cases
like these, ICs with relatively
low levels of integration are of-
ten needed to complete these
circuits.
Where relatively low levels
of integration are employed, it is
found that the package is much
larger than the chip itself. This
results in a very poor utilization
of the board area (also known
as the board’s “real estate”).
To increase the levels of
miniaturization that can be
achieved, one manufacturer has
taken a new look at the way in
which ICs can be packaged.
This has resulted in a new
method of packaging these
small chips so that they take up
Fig.1. Cross section of the chip
size package.
considerably less space on the
board, whilst retaining the low
cost of the packaging.
CSP
A company named Shell-
case, located in Jerusalem, Israel,
has undertaken development of a
new package. Named a Chip Size
Package (CSP), this new idea
allows chips to be mounted in
simple packages that are little
more than the size of the silicon
itself. Not only is the board area
used kept to a minimum, but so is
the height, and in some applica-
tions this can also be critical. The
wafer level technology employed
in the manufacturing process pro-
duces CSPs that measure be-
tween 300 and 700 microns in
height.
The new package essen-
tially consists of the bare chip
sandwiched between two thin
layers of glass to provide the
environmental protection that is
required. Solder balls deposited
onto contact regions of the
package enable connections to
be made to the chip itself.
These connect to the printed
Copyright © 1999 Wimborne Publishing Ltd and
Maxfield & Montrose Interactive Inc
EPE Online, June 1999 - www.epemag.com - 611
1HZ WHFKQRORJ\ 8SGDWHV
circuit board in the same way
that a ball grid array (BGA)
does today.
Finally, the connection pads
have the solder applied and
melted into the familiar solder
balls that are normally associ-
ated with BGA packages. When
this is complete, the wafers are
diced to produce the individual
chip-sized encapsulated ICs.
made a number of improve-
ments. Compliant layers have
been introduced under the sol-
der balls to reduce stress and a
better passivation layer pre-
vents moisture ingress.
Both of these improvements
will enable the long-term relia-
bility of chips using this package
to be improved. Further details
can be obtained by E-mail from
marketad@shellcase.com
MANUFACTURE
One of the keys to the suc-
cess of the new system is that
the packaging takes place at
wafer level, thereby significantly
reducing the costs. The tech-
nique also uses semiconductor-
like processes, enabling it to be
introduced into fabrication
plants without the levels of in-
vestment required for other pro-
cesses.
The manufacturing process
contains a number of steps and
a representation of the finished
package is shown in Fig.1. First
a thin protective glass layer is
bonded to the active side of the
silicon wafer with an epoxy ad-
hesive. Next the silicon material
between the dies is etched
away, leaving the individual ICs
attached to the glass.
At this stage, the grooves
between the dies are filled with
an inert material and a second
thin glass cover is bonded onto
the other side of the silicon dies.
In this way a complete enclo-
sure is obtained.
Next an organic layer is ap-
plied and patterned. This acts
as a compliant layer underneath
the solder joints when equip-
ment manufacturers place the
CSP onto a board during PCB
assembly.
The connections need to be
added. The first step is
achieved by drawing deep
notches between the dies re-
vealing the cross sections of the
IC connection points. A metal
layer is added to create the con-
nection pads, and create the
connections from the IC termi-
nation points on the chip itself.
The correct pattern for this is
defined using photolithography.
Copyright © 1999 Wimborne Publishing Ltd and
Maxfield & Montrose Interactive Inc
ADVANTAGES
Apart from the obvious ad-
vantages of the reduced pack-
age size, the new CSPs offer a
few other benefits. For high fre-
quency and high-speed applica-
tions, the CSP offers even
shorter lead lengths to reduce
the level of parasitic capaci-
tance and inductance, enabling
the chips to operate to their full
potential. The process also of-
fers excellent thermal dissipa-
tion capabilities. This aspect
needs to be considered for a
number of applications where
heat needs to be removed effi-
ciently for the correct operation
of the chips.
The process is very flexible,
allowing a fast transition from
one product to another merely
by changing the mask set.
Production line flexibility is
particularly important where
small volumes are manufac-
tured. If the changeover or
setup times are long, then these
can add significantly to the
overall costs of the product. A
further cost saving is made by
the fact that the process uses
standard processing techniques
and equipment.
OUTLOOK
This new technique has
been swiftly taken up. Xicor are
now working with Shellcase and
they plan to launch a family of
serial EEPROMs in the near fu-
ture. The joint venture has built
upon the original work under-
taken by Shellcase and has
EPE Online, June 1999 - www.epemag.com - 612

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