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ROLL-UP, ROLL-UP!
Ingenuity is our regular round-up of readers' own
circuits. We pay between $16 and $80 for all material
published, depending on length and technical merit.
We're looking for novel applications and circuit tips, not
simply mechanical or electrical ideas. Ideas must be the
reader's own work
and must not have been submitted
for publication elsewhere.
The circuits shown have
NOT been proven by us.
Ingenuity Unlimited
is open to
ALL abilities, but items for consideration in this column
should preferably be typed or word-processed, with a
brief circuit description (between 100 and 500 words
maximum) and full circuit diagram showing all relevant
component values.
Please draw all circuit schematics
as clearly as possible.
Send your circuit ideas to: Alan Winstanley,
Ingenuity Unlimited,
Wimborne Publishing Ltd., Allen
House, East Borough, Wimborne, Dorset BH21 1PF.
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sented to the runners up.
Superior Heads-Tails Indicator
This Heads-Tails Indicator
(see Fig.1) is superior to other
designs in several ways. It is
random to a fault, needs no
setting up, and operates with a
single pushswitch to display either
red or green on a single LED.
In the circuit diagram of
Fig.1, the oscillator based around
IC1a and IC1b, feeds a rapid train
of pulses via ICIc to IC2a, a D-
type flip-flop. As each pulse is
received, IC2a changes state
from “heads” to “tails” and vice
versa. Within 70 milliseconds,
IC2a receives about 500 pulses,
then timer IC1c stops the clock.
Within a further 20ms, IC1d
switches on transistor TR1, which
causes the tricolour LED D1 to
display either red or green.
The purpose of IC1d/TR1 is
to prevent the differing loads
related to D1 from biasing the
timer IC1c in favor of either
heads or tails. Various factors
Copyright © 1999 Wimborne Publishing Ltd and
Maxfield & Montrose Interactive Inc
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Fig.1. Circuit for a superior Heads-Tails indicator
combine to ensure that the
Superior Heads-Tails Indicator
is virtually completely random.
Rev. Thomas Scarborough
Fresnaye, Cape Town, R.S.A.
of the more useful features of
commercial panels at a fraction
of the cost. The loops marked
as “Zone 1”, “Zone 2” and
“Entry/Exit” (S4, S5, S7) are
normally-closed alarm sensors.
The “Tamper Loop” (S6) is also
a normally-closed tamper
protection circuit.
If Zone 1, for example, was
opened then pin 2 of the OR
Home Alarm System
The circuit diagram in Fig. 2
is a simple home alarm system
panel designed to provide some
EPE Online, July 1998 - www.epemag.com - 675
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Fig.2. Suggested (UK) power supply/charger circuit for the
Home Alarm System
gate ICla would be brought high
via resistor Rl, thus causing
LED D5 to light, and the
monostable IC5 would also be
triggered via transistor TR5.
The relay contacts RLA1 will
close for a period set by VR2.
A triggering circuit,
comprising of TR5 and
capacitor C8, is required
because if the sensor (S4)
connected to the OR gate were
to remain permanently open
(e.g. a broken window strip),
then the alarm would sound
indefinitely. Resistor R16 allows
C8 to discharge a few seconds
after the zone (e.g. a PIR) has
been closed again thus resetting
the alarm.
The three key switches S1
to S3 may take many forms, but
to disarm the alarm they must
be closed and to arm the
system and trigger the exit timer
they must be open. On the
prototype, the “Lock” was a 36-
way Centronics socket and the
“Key” simply a matching plug
with six pins jumpered.
Exit time is provided by
means of IC4, another NE555
monostable timer. With “key
switch” S1 closed (system
disarmed) pin 2 of IC4 is
grounded (0V) thus output pin 3
of the timer is held high. This
output is inverted by IC3c and
fed to one input of IC2a (a 4081
AND gate), the output of which
connects to the set input of the
Copyright © 1999 Wimborne Publishing Ltd and
Maxfield & Montrose Interactive Inc
bistable latch formed by IC3a and
lC3b. Assuming the Exit timer IC4
has timed out then pin 2 of IC2a
will be high but pin l will be low
(Exit/Entry zone closed).
Upon opening of the entry/exit
zone the bistable will be set, thus
bringing its Q output (pin 4 of IC3b)
high. This begins to charge
capacitor C3 to give an entry time
of about 17 seconds before pin 5 of
ICla is brought high. If the key is
inserted during this interval then
the Alarm Bell Timer (IC5) is
disabled, the exit timer re-
established and the bistable is
reset. If not then the alarm sounds
as before. Capacitor C4 provides
power on reset for the bistable and
the LEDs. Dl to D4 provide visual
indication of zone status.
A power supply circuit capable
of charging a lead acid battery is
shown separately in Fig.3b. The
alarm circuit could easily be
modified to accept more zones by
the use of the second OR gate in
the 4072 package.
Damien Maguire
Co. Wicklow, Ireland
EPE Online, July 1998 - www.epemag.com - 676
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EPE Online, July 1998 - www.epemag.com - 677
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Plik z chomika:
fred1144
Inne pliki z tego folderu:
0799g(2).pdf
(220 KB)
0799f(2).pdf
(189 KB)
0799m(2).pdf
(399 KB)
0799h(2).pdf
(185 KB)
0799i(2).pdf
(254 KB)
Inne foldery tego chomika:
1999_01
1999_02
1999_03
1999_04
1999_05
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