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By ERNEST FLINT

)520 WR 3(17,80 ,,,

Tracking the Intel

microprocessor to

its lair!

I’ll see your Pentium II

and Raise you Two

Celerons!

In the not-so-distant past,

very few people had the faintest

clue as to which type of micro-

processor was ensconced in

their personal computer (PC).

Instead, in the early days, con-

sumers purchased computers

by type, such as an IBM PC-AT

or PC-XT. Even for those who

did have a clue what was “under

the hood”, the playing field was

fairly easy to understand, as

things tended to progress in a

fairly leisurely and obvious

manner. Each new generation

was faster and better than the

one before and, more impor-

tantly, each new generation

quickly

replaced

the previous

one “on the store shelves”.

By comparison, it’s now

hard to turn on the television

without being accosted with yet

another “Intel Inside” advert. In

fact, those little rapscallions

at Intel are rolling

out new types of

8086

micropro-

there are now multiple concur-

rent architectures targeted at

different markets.

It was bad enough when all

we had to contend with was the

choice between a Pentium and

a Pentium with MMX. Suddenly,

as if from nowhere, we were be-

ing barraged with the additional

options of Celerons, Pentium

IIs, and Pentium II Xeons. And

now we are staring Pentium IIIs

Fig.2. The Pentium processor in

and Pentium III Xeons in the

a Socket 7 configuration.

face, desperately trying not to

(Photo Courtesy of Intel Corp.)

be the first to blink.

In fact there are now so

many flavors of microprocessor

on the loose (each of which is

available in a range of clock fre-

quencies), that even those of us

who are “in the trade” are begin-

ning to lose whatever tenuous

grip we once had on real-

ity. So in this article we

Pentium

will rend the veils asun-

der and expose the hor-

rors within.

Pentium III Xeon

Pentium II Xeon

Pentium III

Pentium II

Pro

Celeron

Pentium w MMX

Fig.1. The evolution of Intel

processors.

1971 (in fact the 4004 was origi-

nally called a microcomputer,

and the term microprocessor

wasn’t coined until sometime

later). The 4004 contained only

2,300 transistors and performed

60,000 operations per second.

The “4”s in the 4004’s name

were intended to reflect the fact

that it had a 4-bit data bus. The

4004 was followed in 1972 by

the 8008, which was pretty

much the same sort of thing, but

with an 8-bit data bus (and

Pentium

486

386

286

THE EARLY

DAYS

8088

8008

4004

4040

8080

cessors so

fast it makes

one’s head spin.

Even worse,

Before we plunge too

deep into the quagmire of to-

day’s microprocessor product

offerings, it is advantageous to

consider the path by which we

arrived at where we are (Fig.1).

The world’s first micropro-

cessor

the 4004

was pre-

sented to the market by Intel in

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3,300 transistors). The 4004

was also enhanced to form the

4040, which contained addi-

tional logical and compare in-

structions and a small internal

stack.

The 4004, 4040, and 8008

were all interesting, but they

were also all designed with spe-

cific applications in mind, and it

wasn’t until 1974 that the 4040

and 8008 evolved into the 8080,

which contained 4,500 transis-

tors and could perform 200,000

operations per second. The

8080 was the first truly general-

purpose microprocessor, and

was destined to become the

central processor for many of

the early home computers.

By 1978, the 8080 had

evolved into the more sophisti-

cated 8-bit 8088 and the 16-bit

8086. The 8088 was to become

pivotal in the history of micro-

processors as we know it, be-

cause IBM decided to use this

as the CPU in what is now con-

sidered to be the first true PC,

which was presented to the

market in 1981.

Cache

L2 Cache bus

(1/2 system clock)

Host/processor bus

(66 MHz)

A Brief Overview of

Technical Terms

During the course of this

article, one or two terms are

mentioned, such as “cache”,

“host bus,” MMX, and so forth.

For those amongst us who

aren’t too familiar with these

(and certain other) terms, a brief

overview is presented here.

CPU

Fig.3. The Pentium Pro ar-

chitecture (two chips in a

multichip module).

SRAM vs DRAM

Semiconductor memory

comes in a variety of flavors.

The two main categories are

read-only memory (ROM) and

random-access memory (RAM).

(The purists amongst us would

prefer to replace the term RAM

with read-write memory (RWM),

but realistically this is never go-

ing to happen).

ROM devices contain in-

structions and/or data that is

“hard-wired” into them during

their construction. By compari-

son, RAM devices only contain

whatever data and instructions

the computer last wrote into

them (and they “forget” their

contents when power is re-

moved from the system).

Furthermore, RAM is itself

split into two core technologies,

which are known as Static RAM

(SRAM) and Dynamic RAM

(DRAM). Each memory cell in

an SRAM device requires be-

tween 4 and 6 transistors, while

each cell in a DRAM device re-

quires only one transistor (so

you can get more memory in a

DRAM device). SRAMs are

faster than DRAMS, but they

use more power, run a lot get

hotter, and are much more ex-

pensive. Thus, the bulk of a

computer’s main memory is

formed from DRAM

devices, and SRAMs are

only used where extreme speed

is required.

Cont...

THE MIDDLE

KINGDOM

In 1982, Intel released the

16-bit 286 microprocessor (also

known as the 80286). With

134,000 transistors, the 286

sported approximately three

times the performance of other

16-bit processors of the time.

Amongst other things, the 286

provided “backwards compati-

bility”, which meant it could run

programs that had been written

for its predecessors. This was

considered to be a pretty revo-

lutionary concept at the time.

Fig.4. The Pentium II shown in a Slot 1 configuration.

(Photo Courtesy of Intel Corp.)

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The 16-bit 286 was followed

by the 32-bit 386 in 1985. This

device, which contained

275,000 transistors, was de-

signed to support “multitasking”

(running multiple programs at

the same time). In turn, the 386

was followed in 1989 by the

486, which contained an amaz-

ing (for the time) 1.2 million

transistors. In the early days,

complex math functions

(multiplication and division)

were performed as a series of

simple steps, such as “shift-and-

add” algorithms. Later schemes

employed external math copro-

cessor devices, which were spe-

cial units dedicated to perform-

ing complex math functions as

quickly as possible. The 486’s

1.2 million transistors allowed it

to include an on-chip math co-

processor as part of the main

CPU (this was considered to be

mega-cool by those of us who

cared).

The first 486s had system

clocks (see sidebar) running at

25 MHz. These were soon fol-

lowed by 33MHz and 66MHz

versions (and various “clock

doublers” appeared later in the

market).

THE GOLDEN AGE

The start of the current

golden age of microprocessors

(insofar as this article is con-

cerned) occurred in 1993, when

Intel first introduced the Pen-

tium processor (Fig.2). With 3.1

million transistors, the Pentium

was approximately five times

faster than its 486 ancestor. The

Pentium sported a 16KBL1

cache (see sidebar) and up to

512KB L2 cache (this L2 cache

was mounted on the main moth-

erboard). The first Pentiums

started with clock speeds of 75

MHz, and over time additional

clock speed options were added

up to the 233 MHz versions of

the present (note that even

though the main clock fre-

quency increased, the host bus

speed remained at 66MHz –

see sidebar). Also, the Pentium

was presented in a pin grid ar-

ray (PGA) package, which

plugged into an Intel-defined

pinout format called “Socket 7”.

The next major develop-

ment occurred in 1995 with the

Pentium Pro, which sported a

number of innovations and im-

provements (and a whopping

5.5 million transistors).

Quite apart from anything

else, the Pentium Pro was pre-

SIMMs vs DIMMS

Multiple memory devices

are typically mounted on small

PCBs (known affectionately as

“sticks” of memory). These are

referred to as SIMMs (single

inline memory modules) if they

only have chips on one side, or

DIMMS (dual inline memory

modules) if they have chips on

both sides.

FDO vs EDO vs SDRAM

vs …..

As was previously noted,

the bulk of a computers RAM is

composed of DRAM devices,

but these can be presented in

different ways. When you pur-

chased a computer in the not-

so-distant past, it came with

FDO (fast data out) memory.

This was subsequently replaced

in later systems by EDO

(extended data out) memory,

which was in turn superceded

by SDRAM (synchronous

DRAM) memory.

This is a bit confusing at

first, but underneath it’s really

quite simple. These memory

schemes are all basically

formed around a core of stan-

dard DRAM chips, but each

uses a different way of control-

ling and accessing the devices

to squeeze more “throughput”

out of them.

Also, note that the term

ECC (error correcting and con-

trol) memory used in higher-end

machines refers to the fact that

these memory devices contain

additional bits that can be used

to detect (and correct) errors in

the data.

Cache

Tag

RAM

Cache

CPU

L2 Cache bus

(1/2 system clock)

Host/processor bus

66 MHz (later 100 MHz)

Fig.5. The Pentium II architecture.

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L1 vs L2 Cache

Modern semiconductor

memories are extremely fast,

Cont...

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sented as a multichip module

package containing two silicon

chips: the Pentium Pro proces-

sor itself (with a 16-kilobyte on-

chip L1 cache) and an L2 cache

chip. The original Pentium Pros

came equipped with 256KB L2

caches, and 512KB versions

became available later. One

really cunning innovation asso-

ciated with the Pentium Pro was

that it had two busses (an exter-

nal processor-to-main-memory

(host) bus and an internal

processor-to-L2-cache bus) and

the processor could access both

busses simultaneously (Fig.3).

The original Pentium Pros

supported a 150 MHz system

clock, and this was quickly fol-

lowed by 200 MHz versions.

The multichip module of the

Pentium Pro allowed the pro-

cessor core and the L2 cache to

be located very close to each

other, which in turn facilitated

the cache bus running at 1/2 the

main system clock frequency.

(This was much faster than the

Pentium’s L2 cache, which was

located on the motherboard,

and which was therefore obliged

to run at the 66MHz host bus

frequency.)

The end result of this dual-

bus architecture (plus other cun-

ning stuff that’s too complex to

go into here) made the Pentium

Pro go “like a bat out of hell.”

The Pentium Pro module

plugged into an Intel-defined

pinout format called “Socket 8”.

The pace really started to

pick up in 1997, when Intel in-

troduced two new develop-

ments. The first was the con-

cept of MMX instructions (see

sidebar), which first appeared in

the “Pentium with MMX.” The

second was the Pentium II pro-

cessor (with a mind-boggling

7.5 million transistors), which

also included MMX instructions

(Fig 4).

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At a first glance, the Pen-

tium II appeared to be radically

different to the Pentium Pro,

because it was presented in a

relatively large package called a

single-edge-connect (SEC) car-

tridge, which plugged into a new

Intel-proprietary socket configu-

ration called Slot 1 on the moth-

erboard.

Internally, the Pentium II is

constructed as a hybrid using a

printed circuit board substrate.

This circuit board contains the

processor chip, which is essen-

tially a Pentium Pro with a 32KB

L1 cache and MMX instruction

support. This board also con-

tains four industry-standard

burst-static cache RAM devices

and a tag RAM chip, which to-

gether form the 512KB L2

cache (Fig.5).

(Note that Fig.5 is only an

illustration. In reality, the pro-

cessor core and two of the

cache RAM devices are

mounted on one side of the

board, while the remaining

cache RAMs and the Tag RAM

are mounted on the other side.)

The first Pentium IIs sup-

ported clock frequencies of 233

and 266 MHz. These were

quickly followed by 300 MHz,

333MHz, and 350 MHz ver-

sions, which were in turn su-

perceded by 400 MHz and 450

MHz options. This obviously has

a huge impact on processor op-

erations, and also cache-

intensive operations (because

the Pentium II cache is running

at 1/2 of the main clock fre-

quency). Furthermore, the first

Pentium IIs supported a host/

processor bus frequency of

66MHz, but this was boosted up

to100MHz in later versions,

which dramatically improved

access to the main memory.

Last but not least, the Pen-

tium II supported Intel’s AGP

but computer programs typically

perform a humongous amount

of memory accesses (reads and

writes), so anything that can be

done to speed things up is gen-

erally considered to be very de-

sirable.

If we analyze programs, we

tend to find that they are often

composed of blocks of instruc-

tions, where each block may be

performed multiple times before

moving onto the next block. A

key point is that these blocks of

instructions tend to be relatively

small compared to the size of

the total program.

Computer designers can

take advantage of this knowl-

edge by creating a special

“chunk” of high-speed memory

called the cache. When the

CPU starts running a program

and it reads an instruction (or

data) for the first time, in addi-

tion to processing that instruc-

tion it also stores it in the cache.

The next time the CPU attempts

to read that instruction (or data),

it first checks to see if it’s al-

ready in the cache

if so it can

read it from the cache much

faster than it could from the

main memory.

The cache is formed from

the fastest SRAM devices avail-

able, but the designer (who

would ideally prefer as large a

cache as possible) has to keep

it smaller than he or she would

like to balance cost, perfor-

mance, and power consump-

tion.

In fact computer designers

typically use a hierarchy of

memory. The L1 (“Level 1”)

cache is very small, but very,

very fast, because it is con-

structed as an integral part of

the CPU itself (on the same sili-

con chip). The L2 (“Level 2”)

cache is significantly bigger

Cont...

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(advanced graphics port). Actu-

ally, to be more precise, it’s the

Pentium II’s supporting chipset

that provides AGP capability,

but supporting chipsets are part

of a completely different discus-

sion, so we’ll ignore them in this

article (for which you can be

truly thankful). The AGP is also

outside the scope of this discus-

sion, except to say that it is de-

signed to streamline the transfer

of data from the CPU to AGP-

compatible graphics accelerator

cards.

face) to be relatively well or-

dered. The 268 was followed by

the 386, which was in turn fol-

lowed by the 468. The 486 be-

got the Pentium, which led to

the Pentium Pro, which in turn

paved the way for the Pentium

II. And then things began to get

complicated …

In 1998, Intel introduced the

Celeron processor, which was

based on the Pentium II. The

first Celerons didn’t have any L2

cache at all, which caused

some observers to refer to them

“brain dead Pentium IIs.”

Subsequent implementations

had 128KB L2 caches, and it

than the L1 cache, but it’s

father away from the CPU and

thus not as fast. (In fact some

computers have L1, L2, and L3

caches between the CPU and

the main memory!)

System Clock vs Host

Bus

The main system clock is

used to synchronize the internal

actions of the CPU and also the

rest of the system. The CPU

communicates with the rest of

the system by means of the

main system bus, which may

also be referred to as the “host

bus”, the “processor bus”,

or the “front bus.”

Increasing the fre-

quency of the system

clock increases the rate

by which the CPU per-

forms its internal actions.

However, the frequency

of the host bus is not di-

rectly related to the fre-

quency of the main sys-

tem clock.

AND THEN …

For a long time things had

appeared (at least on the sur-

Table.1. Summary of Intel microprocessor development

1971

1972

1974

1978

1982

1985

1989

1993

4004

8008

4040

8080

8088/8086

286

386

486

Pentium

2,300 transistors, 4-bit, 60,000 operations per second

3,300 transistors, 8-bit

4-bit (like a 4004 but with additional instructions)

4,500 transistors, 8-bit, 200,000 operations per second

8-bit/16-bit (the 8088 was used in the first IBM PC)

134,000 transistors, 16-bit

275,000 transistors, 32-bit (multitasking)

1.2 million transistors, 32-bit (first math coprocessor)

25MHz system clock (-> to 66MHz over time)

3.1 million transistors, 32-bit, 16KB L1, 512KB L2 (external)

75MHz system clock (-> 233MHz), 66MHz host bus, Socket 7

5.5 million transistors, 32-bit, 16KB L1, 256KB L2 (internal)

150MHz system clock (-> 200MHz), 66MHz host bus

L2 Cache bus runs at 1/2 main system clock, Socket 8

7.5 million transistors, 32-bit, 32KB L1, 512KB L2, MMX

233MHz system clock (-> 500MHz), 66MHz host bus (-> 100MHz)

L2 Cache bus runs at 1/2 main system clock

Overclocking

In order to under-

stand the concept of

overclocking, we first

need to know that com-

puter motherboards are

designed to support a

range of system clock

frequencies. This allows

a Pentium II mother-

board, for example, to

support say 350, 400,

and 450 MHz versions of

the processor. Theoreti-

cally, this allows end-

users to upgrade their

main processor (although

this rarely happens in

practice).

Most Intel processors

are reasonably robust.

Cont..

1995

Pentium Pro

1997

Pentium II

1998

Celeron

7.5 million transistors, 32-bit, 32KB L1, 0KB L2 (later 128KB L2), MMX

266MHz system clock (-> 400MHz), 66MHz host bus

L2 Cache (when provided) bus runs at 1/2 main system clock

7.5 million transistors, 32-bit, 32KB L1, 512KB / 1MB / 2MB L2, MMX

400MHz system clock (-> 500MHz), 100MHz host bus

L2 Cache bus runs at FULL main system clock

7.5 million transistors, 32-bit, 32KB L1, 512KB L2, MMX II

500MHz system clock (-> 550MHz), 100MHz host bus

L2 Cache bus runs at 1/2 main system clock

7.5 million transistors, 32-bit, 32KB L1, 512KB / 1MB / 2MB L2 MMX II

500MHz system clock (-> 550MHz), 100MHz host bus

L2 Cache bus runs at FULL main system clock

1998

Pentium II Xeon

1999

Pentium III

1999

Pentium III Xeon

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