2 Mbps Powerline Network Controller.pdf

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Preliminary
IPL0201 ASIC Data Sheet
IPL0201
FEATURES
2 Mbps Powerline Network Controller
2 Mbps Integrated Powerline Networking MAC/PHY
EXT_ADDR[0:15]
INARI
IPL0201
P0[0-7]
P1[0-7]
P2[0-7]
P3[0]
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Inari’s Digital Powerline (DPL ) Transceiver
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Customized for powerline environment
Includes 4 channel transceiver
Variable data rates up to 2 Mbps
TM
EXT_DATA[0:7]
PSENn
RDn
WRn
SERIAL_IN
PER_CS0n
SERIAL_OUT
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Microcontroller
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8051 instruction set compatible
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Industry standard development tools
8-10 MIPS
4 clock/instruction cycle
Three 8-bit I/O ports
Two 8-bit timer/counters
256 bytes scratchpad RAM
2 KB buffer RAM
Addresses 64 KB external ROM and 64
KB external RAM
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PER_CS1n
EXT_INT0n
EXT_INT1n
RX_DATA0
RX_DATA1
RX_DATA2
CLK
RESETn
TEST
RX_DATA3
DAC_DATA[0:9]
PDAA_CTL
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Generic Host Application Interface
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Two programmable chip selects
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Two external interrupt inputs
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Non-multiplexed address/data bus
Can be used as a “bridge” to other
protocols using external peripherals
Parallel Port (IEEE 1284) software
handshake component
USB firmware support interfacing to the
Philips PDIUSBD12D
Generic Inari adapted Common
Application Language (iCAL) interface
Inari’s Powerline Exchange (PLX)
Embedded Protocol
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Firmware Application Programming
Interfaces (APIs) including QoS
MAC layer packet pacing (throttling)
Guaranteed time slots for isochronous
communications
32-bit device addressing capabilities
Automatic transmit packet formatting
Automatic address recognition and
packet reception
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Security and Error Detection
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32-byte encryption array
256-bit Diffie-Hellman public key
exchange
Packet level authentication
16-bit hardware CRC
Version 0.95
Inari, Inc. Proprietary
Use pursuant to Company Instructions
1
IPL0201 ASIC Data Sheet
Preliminary
1 Overview of the IPL0201 Chip
The IPL0201 ASIC is a primary component in a
high-speed, low cost networking solution that
allows devices to communicate using ordinary
powerlines as the transmission media. Figure 1
depicts an overview of this system.
The IPL0201 connects to the powerline through
an external
Powerline Data Access
Arrangement
(PDAA). Line coupling
components isolate the powerline’s high voltage.
Data is transmitted via four modulated carriers
using binary phase-shift keying or quadrature
phase-shift keying.
In the transmit direction, the PDAA is comprised
of filters and a linear line driver. In the receive
direction, the PDAA separates the receive signal
into four carriers, which are then mixed with four
local oscillator signals to generate four signals.
These signals are driven to the IPL0201
receiver
.
IPL0201
Ports
Microcontroller
Interface
Receiver
Powerline Data
Access
Arrangement
Buffer RAM
Powerline
Connection
8051
Transmitter
ROM
External Bus
= DMA
= 8051 moves
Figure 1 – IPL0201 Data Flow Block Diagram
The system is supervised by an internal 8051
microcontroller. The 8051 controls all the
elements of the IPL0201 and executes code
from an external ROM. The 8051 is supported
by the microcontroller interface block, which is a
collection of functions supporting data flow.
In the IPL0201, the microcontroller interface is
also responsible for moving data on and off chip.
The 8051 reads data to be transmitted from
external
peripherals connected to the ports or external
data bus and stores this data in the on-board
buffer RAM. Then, the microcontroller interface
activates the transmitter block, which transfers
the data without processor intervention. For
receive data, the receiver block places data
directly into the buffer RAM, then interrupts the
8051, which in turn formats the data for transfer
to external peripherals.
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Inari, Inc. Proprietary
Use pursuant to Company Instructions
Version 0.95
Preliminary
Transmitter
The 8051 assembles data to be transmitted
in the buffer RAM and commands the
transmission to begin. The transmitter
hardware handles all tasks of transmission
until they are completed, transmitting four
channels of data simultaneously on the
powerline.
Each byte of data is converted from parallel
to serial form and encoded into differential
phase shift keying (PSK). Two types of
modulation are supported: binary phase-shift
keying, or quadrature phase-shift keying at
selectable symbol times.
The transmitter is responsible for sending
the preamble, encrypting the packet (if
enabled), and generating a 16-bit CRC. The
CRC is appended to and sent at the end of
the packet.
The transmitter interrupts the 8051 with a
transmit packet interrupt after all four
packets are sent.
1.1 Receiver
The receive data is driven to the IPL0201 as
four digital input signals, one for each carrier
used on the powerline, extracted by the
PDAA. The IPL0201 receives all channels in
parallel.
The 8051 is not involved with the actual
reception of packets beyond enabling them
to begin.
A valid packet consists of a valid preamble
and a destination address to which this node
responds.
Each byte of data is decrypted as it is
received (if decryption is enabled by the
8051, and if the packet is marked as an
encrypted packet). The packet’s data is also
checked against its CRC.
Each data byte is stored in the internal
buffer RAM for later access by the 8051.
IPL0201 ASIC Data Sheet
After a valid packet is received, a receive
packet interrupt is generated. After a
successful reception, the hardware stops
hunting for new receive packets.
The receiver gives status about each
channel which is guaranteed valid after a
receive packet interrupt is generated. The
status stays valid until the receiver is again
enabled to receive packets.
Status shows which address match
occurred, which errors occurred in the
reception of the packet, and at what symbol
time the packet was received.
1.2 Microcontroller Interface
The microprocessor interface contains the
registers necessary to interface the 8051
microcontroller with the buffer RAM,
receiver, and transmitter modules. It also
interfaces the 8051 with external ports and
external peripherals.
1.3 8051
The microcontroller core runs the standard
8051 instruction set. It provides similar
resources to the standard 8051 including
timers, a full-duplex asynchronous serial
port, and 256 bytes of scratchpad memory.
It runs a machine cycle in 4 clock cycles
(versus 12 clock cycles for a standard
8051). The Inari firmware uses some 8051
resources.
1.4 Firmware APIs
The IPL0201 comes with a PLX firmware
kernel, which interfaces with the hardware.
Packets are sent and received under
direction of this kernel.
Customized applications can be written
using the provided PLX APIs to access core
protocol (kernel) functions.
Version 0.95
Inari, Inc. Proprietary
Use pursuant to Company Instructions
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