ADG728.PDF

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FEATURES
Two Wire Serial Interface
+2.7 V to +5.5 V Single Supply
Low On Resistance (4
Ω
)
Low On Resistance Flatness
Low Leakage
Single 8 to 1 Matrix Switch ADG728
Dual 4 to 1 Matrix Switch ADG729
Power On Reset
Fast Switching Times
Low Power Consumption
CMOS, Low Voltage, 2 Wire,
Serially Controlled Matrix Switches
ADG728/ADG729
Preliminary Technical Data
FUNCTIONAL BLOCK DIAGRAMS
ADG728
S1
S1A
DA
S4A
D
ADG729
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay replacement
Audio and Video Switching
GENERAL DESCRIPTION
The ADG728 and ADG729 are CMOS analog matrix
switches with a serially controlled two wire interface. The
ADG728 is an 8 channel matrix switch, while the
ADG729 is a dual 4 channel matrix switches. On
resistance is closely matched between switches and very
flat over the full signal range. These parts can operate
equally well as either Multiplexers, De-Multiplexers or
Switch arrays and the input signal range extends to the
supplies.
The ADG728 and ADG729 utilize a two wire serial
interface that is compatible with the I
2
C
TM
interface
standard. Both have two external address pins (A0 and
A1). This allows the 2 LSB’s of the 7-bit slave address to
be set by the user. Four of each devices can be connected
to the one bus. The ADG728 also has a
RESET
pin, this
should be tied high if not in use.
Y
R
A
IN AL
IM IC
L N
E H
R C
P E
TA
T DA
S8
INPUT REGISTER
S1B
DB
S4B
INPUT REGISTER
RESET
SDA
SCL A0
A1
SDA
SCL
A0
A1
On power up of the device, all switches will be in the
OFF condition and the internal shift register will contain
all zeros.
All channels exhibit break before make switching action
preventing momentary shorting when switching channels.
The ADG728 and ADG729 are available in a 16 lead
TSSOP package.
PRODUCT HIGHLIGHTS
1. Two Wire Serial Interface.
2. Single Supply Operation. The ADG728 and ADG729
are fully specified and guaranteed with +3 V and +5 V
supply rails.
3. Low R
ON
(4
Ω).
4. Any configuration of switches may be on at any one
time.
5. Break before make switching action.
6. Small 16 lead TSSOP package.
Each channel is controlled by one bit of an 8 bit word.
This means that these devices may be used in a number of
different configurations, all, any or none of the channels
may be on at any one time.
I
2
C is a trademark of Philips Corporation.
REV. PrC August ‘99
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A.
.O.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
ADG728/ADG729–SPECIFICATIONS
Parameter
ANALOG SWITCH
Analog Signal Range
On-Resistance (R
ON
)
On-Resistance Match Between
Channels (∆R
ON
)
On-Resistance Flatness (R
FLAT(ON)
)
LEAKAGE CURRENTS
Source OFF Leakage I
S
(OFF)
Drain OFF Leakage I
D
(OFF)
B Version
–40°C
o
+25 C
to +85°C
1
(V
DD
= +5 V ±10%, GND = 0 V)
Units
V
Ω
Ω
Ω
Ω
Ω
Ω
Test Conditions/Comments
0 V to V
DD
2.5
4
4.5
0.1
0.4
1.2
±0.01
±0.1
±0.01
±0.1
±0.01
±0.1
0.75
typ
max
typ
max
typ
max
typ
max
typ
max
typ
max
V
S
= 0 V to V
DD
, I
S
= 10 mA;
Test Circuit 1;
V
S
= 0 V to V
DD
, I
S
= 10 mA;
V
S
= 0 V to V
DD
, I
S
= 10 mA;
±0.3
±0.3
Channel ON Leakage I
D
, I
S
(ON)
LOGIC INPUTS (A0, A1)
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current
I
INL
or I
INH
Cin, Input Capacitance
LOGIC INPUTS (SCL, SDA)
2
Input High Voltage, V
INH
Input Low Voltage, V
INL
I
IN
, Input Leakage Current
V
HYST
, Input Hysteresis
C
IN
, Input Capacitance
LOGIC OUTPUT (SDA)
2
V
OL
, Output Low Voltage
2
Y
R
A
IN AL
IM IC
L N
E H
R C
P E
TA
T DA
±0.3
2.4
0.8
V min
V max
0.005
±0.1
3
µA typ
µA max
pF typ
V min
Vmax
V min
V max
µA
typ
µA
max
V min
pF typ
0.7V
DD
V
DD
+0.3
-0.3
0.3V
DD
±TBD
TBD
0.05V
DD
3
0.4
0.6
30
TBD
21
TBD
15
1
5
-60
-80
200
TBD
TBD
TBD
10
TBD
V max
V max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
µA typ
µA max
nA
nA
nA
nA
nA
nA
V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V;
Test Circuit 2;
V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V;
Test Circuit 2;
V
D
= V
S
= 1 V, or 4.5V;
Test Circuit 3;
V
IN
= 0V to V
DD
.
I
SINK
= 3 mA
I
SINK
= 6 mA
R
L
= 300
Ω,
C
L
= 35 pF;
V
S
= 3 V, Test Circuit 4;
R
L
= 300
Ω,
C
L
= 35 pF;
V
S
= 3 V, Test Circuit 4;
R
L
= 300
Ω,
C
L
= 35 pF
V
S1
= V
S2
= 3 V, Test Circuit 5
V
S
= 2 V, R
S
= 0
Ω,
C
L
= 1 nF;
Test Circuit 5;
R
L
= 50
Ω,
C
L
= 5 pF, f = 10MHz;
Test Circuit 6;
R
L
= 50
Ω,
C
L
= 5 pF, f = 10MHz;
Test Circuit 7;
R
L
= 50
Ω,
C
L
= 5 pF, Test Circuit 6;
DYNAMIC CHARACTERISTICS
2
t
ON
t
OFF
Break-Before-Make Time Delay, t
D
Charge Injection
Off Isolation
Crosstalk
-3 dB Bandwidth
C
S
(OFF)
C
D
(OFF)
C
D
, C
S
(ON)
POWER REQUIREMENTS
I
DD
V
DD
= +5.5 V
Digital Inputs = 0 V or 5.5 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. PrC
ADG728/ADG729–SPECIFICATIONS
Parameter
ANALOG SWITCH
Analog Signal Range
On-Resistance (R
ON
)
On-Resistance Match Between
Channels (∆R
ON
)
On-Resistance Flatness (R
FLAT(ON)
)
LEAKAGE CURRENTS
Source OFF Leakage I
S
(OFF)
Drain OFF Leakage I
D
(OFF)
Channel ON Leakage I
D
, I
S
(ON)
LOGIC INPUTS (A0, A1)
2
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current
I
INL
or I
INH
Cin, Input Capacitance
+25 C
o
1
(V
DD
= +5 V ±10%, GND = 0 V)
Units
V
Ω
Ω
Ω
Ω
Ω
Test Conditions/Comments
–40°C
to +85°C
0 V to V
DD
5
8
0.4
2.5
4.5
0.1
typ
max
typ
max
max
typ
max
typ
max
typ
max
V
S
=
Test
V
S
=
V
S
=
0 V to V
DD
, I
S
= 10 mA;
Circuit 1;
0 V to V
DD
, I
S
= 10 mA;
0 V to V
DD
, I
S
= 10 mA;
LOGIC INPUTS (SCL, SDA)
2
Input High Voltage, V
INH
Input Low Voltage, V
INL
I
IN
, Input Leakage Current
V
HYST
, Input Hysteresis
C
IN
, Input Capacitance
LOGIC OUTPUT (SDA)
2
V
OL
, Output Low Voltage
Y
R
A
IN AL
IM IC
L N
E H
R C
P E
TA
T DA
±0.3
2.0
0.4
V min
V max
0.005
±0.1
3
µA typ
µA max
pF typ
V min
Vmax
V min
V max
µA
typ
µA
max
V min
pF typ
0.7V
DD
V
DD
+0.3
-0.3
0.3V
DD
TBD
±TBD
0.05V
DD
3
0.4
0.6
35
TBD
27
TBD
15
1
5
-60
-80
200
TBD
TBD
TBD
10
TBD
V max
V max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
µA typ
µA max
±0.01
±0.1
±0.01
±0.1
±0.01
±0.1
±0.3
±0.3
nA
nA
nA
nA
nA
nA
V
DD
= +3.3 V
V
S
= 3 V/1 V, V
D
= 1 V/3 V;
Test Circuit 2;
V
S
= 1 V/3 V, V
D
= 3 V/1 V;
Test Circuit 2;
V
S
= V
D
= +1 V or +3 V;
Test Circuit 3;
V
IN
= 0V to V
DD
.
I
SINK
= 3 mA
I
SINK
= 6 mA
R
L
= 300
Ω,
C
L
= 35 pF;
V
S
= 2 V, Test Circuit 4;
R
L
= 300
Ω,
C
L
= 35 pF;
V
S
= 2 V, Test Circuit 4;
R
L
= 300
Ω,
C
L
= 35 pF
V
S1
= V
S2
= 2 V, Test Circuit 5
V
S
= 1.5 V, R
S
= 0
Ω,
C
L
= 1 nF;
Test Circuit 5;
R
L
= 50
Ω,
C
L
= 5 pF, f = 10 MHz;
Test Circuit 6;
R
L
= 50
Ω,
C
L
= 5 pF, f = 10MHz;
Test Circuit 7;
R
L
= 50
Ω,
C
L
= 5 pF, Test Circuit 6;
DYNAMIC CHARACTERISTICS
2
t
ON
t
OFF
Break-Before-Make Time Delay, t
D
Charge Injection
Off Isolation
Crosstalk
-3 dB Bandwidth
C
S
(OFF)
C
D
(OFF)
C
D
, C
S
(ON)
POWER REQUIREMENTS
I
DD
V
DD
= +3.3 V
Digital Inputs = 0 V or 3.3 V
NOTES
1
Temperature ranges are as follows: B Versions: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. PrC
–3–
ADG728/ADG729
Preliminary Technical Data
DD
TIMING CHARACTERISTICS
1
(V
Parameter
FSCL
t
1
t
2
t
3
t
4
t
5
t
62
t
7
t
8
t
9
t
10
t
11
C
b
t
SP4
Limit at T
MIN
, T
MAX
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
20 + 0.1C
b3
250
300
20 + 0.1C
b3
400
50
= +2.5 V to +5.5 V . All specifications –40°C to +85°Cunless otherwise noted)
Conditions/Comments
SCL Clock Frequency
SCL Cycle Time
t
HIGH
, SCL High Time
t
LOW
, SCL Low Time
t
HD, STA
, Start/Repeated Start Condition Hold Time
t
SU, DAT
, Data Setup Time
t
HD, DAT
, Data Hold Time
t
SU, STA
, Setup Time for Repeated Start
t
SU, STO
, Stop Condition Setup Time
t
BUF
, Bus Free Time Between a STOP Condition and
a Start Condition
t
R
, Rise Time of both SCL and SDA when receiving
t
F
, Fall Time of SDA when receiving
t
F
, Fall Time of both SCL and SDA when transmitting
Units
kHz max
µs
min
µs
min
µs
min
µs
min
ns min
µs
max
µs
min
µs
min
µs
min
µs
min
NOTES
1
See Figure 1.
2
A master device must provide a hold time of at least 300ns for the SDA signal (referred to the V
IH
min of the SCL signal) in order to bridge the undefined region of SCL’s
falling edge.
3
C
b
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3V
DD
and 0.7V
DD
.
4
Input filtering on both the SCL and SDA inputs suppress noise spikes which are less than 50ns.
Specifications subject to change without notice.
SDA
Y
R
A
IN AL
IM IC
L N
E H
R C
P E
TA
T DA
ns max
ns min
ns max
ns max
ns min
pF max
ns max
t
10
t
11
t
4
t
6
t
2
t
5
t
7
REPEATED
START
CONDITION
Capacitive Load for Each Bus Line
Pulse width of spike suppressed
t
9
t
3
SCL
t
4
START
CONDITION
t
1
t
8
STOP
CONDITION
Figure 1. 2-Wire Serial Interface Timing Diagram.
–4–
REV. PrC
Preliminary Technical Data
PIN FUNCTION DESCRIPTION
ADG728/ADG729
ADG728
1
ADG729
1
Mnemonic Function
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into
the 16-bit input shift register. Clock rates of up to 400kbit/s can be accommodated
with this 2-wire serial interface.
Active low control input that clears the input register and turns all switches to the
OFF condition.
Serial Data Line. This is used in conjunction with the SCL line to clock data into
the 8-bit input shift register during the write cycle and used to read back 1 byte of
data during the read cyle. It is a bidirectional open-drain data line which should be
pulled to the supply with an external pull-up resistor.
Source. May be an input or output.
Drain. May be an input or output.
Source. May be an input or output.
Power Supply Input. These parts can be operated from a supply of +2.5V to +5.5V.
Ground reference.
Address Input. Sets the 2nd Least Significant bit of the 7 bit slave address.
Address Input. Sets the Least Significant bit of the 7 bit slave address.
PIN CONFIGURATIONS
2
3
-
3
RESET
SDA
4,5,6,7
8
9,10,11,12
13
14
15
16
4,5,6,7
8,9
10,11,12,13
14
15
2
16
SXX
DX
SXX
V
DD
GND
A1
A0
SCL
RESET
SDA
Y
R
A
IN AL
IM IC
L N
E H
R C
P E
TA
T DA
ADG728
1
2
3
4
5
6
7
8
16 A0
15 A1
SCL
A1
1
2
ADG729
16
15
14
13
12
A0
GND
V
DD
S1B
S2B
14 GND
13 V
DD
S5
SDA
3
4
5
6
7
8
S1
S2
S3
S4
ADG728
S1A
S2A
S3A
S4A
ADG729
TOP VIEW
(Not to Scale)
12
TOP VIEW
(Not to Scale)
11 S6
S7
S8
11 S3B
10
9
S4B
DB
10
D
9
DA
ORDERING GUIDE
Model
ADG728BRU
ADG729BRU
Temperature Range
-40
o
C to +85
o
C
-40
o
C to +85
o
C
Package Description
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Package Option
RU-16
RU-16
REV. PrC
–5–

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