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HIP6601, HIP6603

Data Sheet

January 2000

File Number

4819

Synchronous-Rectiﬁed Buck MOSFET

Drivers

The HIP6601 and HIP6603 are high frequency, dual

MOSFET drivers speciﬁcally designed to drive two power

N-Channel MOSFETs in a synchronous-rectiﬁed buck

converter topology. These drivers combined with a HIP630x

Multi-Phase Buck PWM controller and Intersil UltraFETs™

form a complete core-voltage regulator solution for

advanced microprocessors.

The HIP6601 drives the lower gate in a synchronous-rectiﬁer

bridge to 12V, while the upper gate can be independently

driven over a range from 5V to 12V. The HIP6603 drives

both upper and lower gates over a range of 5V to 12V. This

drive-voltage ﬂexibility provides the advantage of optimizing

applications involving trade-offs between switching losses

and conduction losses.

The output drivers in the HIP6601 and HIP6603 have the

capacity to efﬁciently switch power MOSFETs at frequencies

up to 2MHz. Each driver is capable of driving a 3000pF load

with a 30ns propagation delay and 50ns transition time. Both

products implement bootstrapping on the upper gate with

only an external capacitor required. This reduces

implementation complexity and allows the use of higher

performance, cost effective, N-Channel MOSFETs. Adaptive

shoot-through protection is integrated to prevent both

MOSFETs from conducting simultaneously.

Features

• Drives Two N-Channel MOSFETs

• Adaptive Shoot-Through Protection

• Internal Bootstrap Device

• Supports High Switching Frequency

- Fast Output Rise Time

- Propagation Delay 30ns

• Small 8 Lead SOIC Package

• Dual Gate-Drive Voltages for Optimal Efﬁciency

• Three-State Input for Bridge Shutdown

• Supply Under Voltage Protection

Applications

• Core Voltage Supplies for Intel Pentium® III, AMD®

Athlon™ Microprocessors

• High Frequency Low Proﬁle DC-DC Converters

• High Current Low Voltage DC-DC Converters

Pinout

HIP6601CB/HIP6603CB

(SOIC)

TOP VIEW

Ordering Information

PART NUMBER

HIP6601CB

HIP6603CB

TEMP. RANGE

(

0 to 85

PACKAGE

8 Ld SOIC

PKG. NO.

M8.15

UGATE

BOOT

PWM

GND

PHASE

PVCC

VCC

LGATE

Block Diagram

PVCC

BOOT

UGATE

VCC

PHASE

+5V

10K

PWM

CONTROL

LOGIC

10K

SHOOT-

THROUGH

PROTECTION

†

VCC FOR HIP6601

PVCC FOR HIP6603

†

LGATE

GND

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

UltraFET™ is a trademark of Intersil Corporation. 1-888-INTERSIL or 321-724-7143

Intersil Corporation 2000

Pentium® is a registered trademark of Intel Corporation. AMD® is a registered trademark of Advanced Micro Devices, Inc.

HIP6601, HIP6603

Typical Application

+12V

+5V

BOOT

VCC

PWM

PVCC

UGATE

DRIVE PHASE

HIP6601

LGATE

+12V

+5V

BOOT

+VCORE

VFB

VCC

VSEN

PGOOD

COMP

VCC

PWM1

PWM2

PWM3

PWM

PVCC

UGATE

DRIVE PHASE

HIP6601

LGATE

VID

MAIN

CONTROL

HIP6301

ISEN1

ISEN2

GND

ISEN3

+5V

BOOT

PVCC

VCC

PWM

DRIVE PHASE

HIP6601

LGATE

UGATE

+12V

HIP6601, HIP6603

Absolute Maximum Ratings

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V

Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V

BOOT Voltage (V

BOOT

- V

PHASE

). . . . . . . . . . . . . . . . . . . . . . . .15V

Input Voltage (V

PWM

) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V

UGATE . . . . . . . . . . . . . . . . . . . . . . V

PHASE

- 0.3V to V

BOOT

+ 0.3V

LGATE . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V

PVCC

+ 0.3V

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV

Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .200V

Thermal Information

Thermal Resistance

(

C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

113

Maximum Junction Temperature (Plastic Package) . . . . . . . .150

Maximum Storage Temperature Range . . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(SOIC - Lead Tips Only)

Operating Conditions

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0

C to 85

Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V

±10%

Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

Electrical Speciﬁcations

PARAMETER

VCC SUPPLY CURRENT

Bias Supply Current

Recommended Operating Conditions, Unless Otherwise Noted

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VCC

PVCC

HIP6601, f

PWM

= 1MHz, V

PVCC

= 12V

HIP6603, f

PWM

= 1MHz, V

PVCC

= 12V

HIP6601, f

PWM

= 1MHz, V

PVCC

= 12V

HIP6603, f

PWM

= 1MHz, V

PVCC

= 12V

4.4

2.5

200

1.8

6.2

3.6

430

3.3

µA

Power Supply Current

POWER-ON RESET

VCC Rising Threshold

VCC Falling Threshold

PWM INPUT

Input Current

PWM Rising Threshold

PWM Falling Threshold

UGATE Rise Time

LGATE Rise Time

UGATE Fall Time

LGATE Fall Time

UGATE Turn-Off Propagation Delay

LGATE Turn-Off Propagation Delay

Shutdown Window

Shutdown Holdoff Time

OUTPUT

Upper Drive Source Impedance

UGATE

LGATE

VCC

= 12V, V

PVCC

= 5V

VCC

= V

PVCC

= 12V

Upper Drive Sink Impedance

VCC

= 12V, V

PVCC

= 5V

VCC

= 12V, V

PVCC

= 12V

Lower Drive Source Impedance

VCC

= 12V, V

PVCC

= 5V

VCC

= 12V, V

PVCC

= 12V

Lower Drive Sink Impedance

VCC

= V

PVCC

= 12V

2.5

7.0

2.3

1.0

4.5

9.0

1.5

3.0

7.5

2.8

1.3

5.0

9.5

2.9

Ω

UGATE

LGATE

UGATE

LGATE

PVCC

= V

VCC

= 12V, 3nF load

PVCC

= V

VCC

= 12V, 3nF load

PVCC

= V

VCC

= 12V, 3nF load

PVCC

= V

VCC

= 12V, 3nF load

PWM

= 0 or 5V (See Block Diagram)

3.6

1.5

500

3.7

1.3

230

1.4

3.6

µA

9.7

9.0

9.9

9.1

10.0

9.2

TPDL

UGATE

VCC

= V

PVCC

= 12V, 3nF load

TPDL

LGATE

VCC

= V

PVCC

= 12V, 3nF load

HIP6601, HIP6603

Functional Pin Description

UGATE (Pin 1)

Upper gate drive output. Connect to gate of high-side power

N-Channel MOSFET.

PVCC (Pin 7)

For the HIP6601, this pin supplies the upper gate drive bias.

Connect this pin from +12V down to +5V.

For the HIP6603, this pin supplies both the upper and lower

gate drive bias. Connect this pin to either +12V or +5V.

BOOT (Pin 2)

Floating bootstrap supply pin for the upper gate drive.

Connect the bootstrap capacitor between this pin and the

PHASE pin. The bootstrap capacitor provides the charge to

turn on the upper MOSFET. See the Internal Bootstrap

Device section under DESCRIPTION for guidance in

choosing the appropriate capacitor value.

PHASE (Pin 8)

Connect this pin to the source of the upper MOSFET and the

drain of the lower MOSFET. The PHASE voltage is

monitored for adaptive shoot-through protection. This pin

also provides a return path for the upper gate drive.

Description

Operation

Designed for versatility and speed, the HIP6601 and HIP6603

dual MOSFET drivers control both high-side and low-side N-

Channel FETs from one externally provided PWM signal.

The upper and lower gates are held low until the driver is

initialized. Once the VCC voltage surpasses the VCC Rising

Threshold (See Electrical Speciﬁcations), the PWM signal

takes control of gate transitions. A rising edge on PWM

initiates the turn-off of the lower MOSFET (see Timing

Diagram). After a short propagation delay [TPDL

LGATE

], the

lower gate begins to fall. Typical fall times [TF

LGATE

] are

provided in the Electrical Speciﬁcations section. Adaptive

shoot-through circuitry monitors the LGATE voltage and

determines the upper gate delay time [TPDH

UGATE

] based

on how quickly the LGATE voltage drops below 1.0V. This

prevents both the lower and upper MOSFETs from

conducting simultaneously or shoot-through. Once this delay

period is complete the upper gate drive begins to rise

[TR

UGATE

] and the upper MOSFET turns on.

PWM (Pin 3)

The PWM signal is the control input for the driver. The PWM

signal can enter three distinct states during operation, see the

three-state PWM Input section under DESCRIPTION for further

details. Connect this pin to the PWM output of the controller.

GND (Pin 4)

Bias and reference ground. All signals are referenced to this

node.

LGATE (Pin 5)

Lower gate drive output. Connect to gate of the low-side

power N-Channel MOSFET.

VCC (Pin 6)

Connect this pin to a +12V bias supply. Place a high quality

bypass capacitor from this pin to GND.

Timing Diagram

PWM

TPDH

UGATE

TPDL

UGATE

LGATE

TPDL

LGATE

TPDH

LGATE

HIP6601, HIP6603

A falling transition on PWM indicates the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

propagation delay [TPDL

UGATE

] is encountered before the

upper gate begins to fall [TF

UGATE

]. Again, the adaptive

shoot-through circuitry determines the lower gate delay time,

TPDH

LGATE

. The PHASE voltage is monitored and the lower

gate is allowed to rise after PHASE drops below 0.5V. The

lower gate then rises [TR

LGATE

], turning on the lower

MOSFET.

The bootstrap capacitor must have a maximum voltage

rating above VCC + 5V. The bootstrap capacitor can be

chosen from the following equation:

GATE

BOOT

≥

-----------------------

∆V

BOOT

Where Q

GATE

is the amount of gate charge required to fully

charge the gate of the upper MOSFET. The

∆V

BOOT

term is

deﬁned as the allowable droop in the rail of the upper drive.

As an example, suppose a HUF76139 is chosen as the

upper MOSFET. The gate charge, Q

GATE

, from the data

sheet is 65nC for a 10V upper gate drive. We will assume a

200mV droop in drive voltage over the PWM cycle. We ﬁnd

that a bootstrap capacitance of at least 0.325µF is required.

The next larger standard value capacitance is 0.33µF.

Three-State PWM Input

A unique feature of the HIP660X drivers is the addition of a

shutdown window to the PWM input. If the PWM signal

enters and remains within the shutdown window for a set

holdoff time, the output drivers are disabled and both

MOSFET gates are pulled and held low. The shutdown state

is removed when the PWM signal moves outside the

shutdown window. Otherwise, the PWM rising and falling

thresholds outlined in the ELECTRICAL SPECIFICATIONS

determine when the lower and upper gates are enabled.

Gate Drive Voltage Versatility

The HIP6601 and HIP6603 provide the user total ﬂexibility in

choosing the gate drive voltage. The HIP6601 lower gate

drive is ﬁxed to VCC [+12V], but the upper drive rail can

range from 12V down to 5V depending on what voltage is

applied to PVCC. The HIP6603 ties the upper and lower

drive rails together. Simply applying a voltage from 5V up to

12V on PVCC will set both driver rail voltages.

Adaptive Shoot-Through Protection

Both drivers incorporate adaptive shoot-through protection

to prevent upper and lower MOSFETs from conducting

simultaneously and shorting the input supply. This is

accomplished by ensuring the falling gate has turned off one

MOSFET before the other is allowed to rise.

During turn-off of the lower MOSFET, the LGATE voltage is

monitored until it reaches a 1.0V threshold, at which time the

UGATE is released to rise. Adaptive shoot-through circuitry

monitors the PHASE voltage during UGATE turn-off. Once

PHASE has dropped below a threshold of 0.5V, the LGATE

is allowed to rise. PHASE continues to be monitored during

the lower gate rise time. If the PHASE voltage exceeds the

0.5V threshold during this period and remains high for longer

than 2µs, the LGATE transitions low. Both upper and lower

gates are then held low until the next rising edge of the PWM

signal.

Power Dissipation

Package power dissipation is mainly a function of the

switching frequency and total gate charge of the selected

MOSFETs. Calculating the power dissipation in the driver for

a desired application is critical to ensuring safe operation.

Exceeding the maximum allowable power dissipation level

will push the IC beyond the maximum recommended

operating junction temperature of 125

C. The maximum

allowable IC power dissipation for the SO8 package is

approximately 800mW. When designing the driver into an

application, it is recommended that the following calculation

be performed to ensure safe operation at the desired

frequency for the selected MOSFETs. The power dissipated

by the driver is approximated as:

1.05f





DDQ





Power-On Reset (POR) Function

During initial startup, the VCC voltage rise is monitored and

gate drives are held low until a typical VCC rising threshold

of 9.9V is reached. Once the rising VCC threshold is

exceeded, the PWM input signal takes control of the gate

drives. If VCC drops below a typical VCC falling threshold of

9.1V during operation, then both gate drives are again held

low. This condition persists until the VCC voltage exceeds

the VCC rising threshold.

Internal Bootstrap Device

Both drivers feature an internal bootstrap device. Simply

adding an external capacitor across the BOOT and PHASE

pins completes the bootstrap circuit.

where f

is the switching frequency of the PWM signal. V

and V

represent the upper and lower gate rail voltage. Q

and Q

is the upper and lower gate charge determined by

MOSFET selection and any external capacitance added to

the gate pins. The I

DDQ

product is the quiescent power

of the driver and is typically 30mW.

The power dissipation approximation is a result of power

transferred to and from the upper and lower gates. But, the

internal bootstrap device also dissipates power on-chip

during the refresh cycle. Expressing this power in terms of

the upper MOSFET total gate charge is explained below.

HIP6601.PDF

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