IntelXScaleTechnologyIntelCoreDevelopersManual-27347302.pdf

(3707 KB) Pobierz
Intel XScale® Core
Developer’s Manual
January, 2004
Order Number: 273473-002
Intel XScale® Core Developer’s Manual
Information in this document is provided in connection with Intel
®
products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Intel
®
internal code names are subject to change.
THIS SPECIFICATION, THE
Intel XScale® Core Developer’s Manual
IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING
ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY
OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. No license,
express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
Copyright © Intel Corporation, 2004
AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic,
DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740,
IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel
NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation,
Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer
logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare,
RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In,
TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and
other countries.
The ARM* and ARM Powered logo marks (the ARM marks) are trademarks of ARM, Ltd., and Intel uses these marks under license from ARM, Ltd.
*Other names and brands may be claimed as the property of others.
2
January, 2004
Developer’s Manual
Intel XScale® Core Developer’s Manual
Contents
Contents
1
Introduction .................................................................................................................................... 13
1.1
About This Document ......................................................................................................... 13
1.1.1 How to Read This Document ................................................................................. 13
1.1.2 Other Relevant Documents ................................................................................... 14
High-Level Overview of the Intel XScale
®
Core..................................................................15
1.2.1 ARM Compatibility .................................................................................................15
1.2.2 Features................................................................................................................. 16
1.2.2.1 Multiply/Accumulate (MAC).................................................................... 16
1.2.2.2 Memory Management ............................................................................ 17
1.2.2.3 Instruction Cache ................................................................................... 17
1.2.2.4 Branch Target Buffer..............................................................................17
1.2.2.5 Data Cache ............................................................................................17
1.2.2.6 Performance Monitoring.........................................................................18
1.2.2.7 Power Management ............................................................................... 18
1.2.2.8 Debug .................................................................................................... 18
1.2.2.9 JTAG ...................................................................................................... 18
Terminology and Conventions ............................................................................................19
1.3.1 Number Representation......................................................................................... 19
1.3.2 Terminology and Acronyms ................................................................................... 19
1.2
1.3
2
Programming Model ......................................................................................................................21
2.1
2.2
ARM Architecture Compatibility ..........................................................................................21
ARM Architecture Implementation Options.........................................................................21
2.2.1 Big Endian versus Little Endian ............................................................................. 21
2.2.2 26-Bit Architecture .................................................................................................21
2.2.3 Thumb....................................................................................................................21
2.2.4 ARM DSP-Enhanced Instruction Set ..................................................................... 22
2.2.5 Base Register Update............................................................................................22
Extensions to ARM Architecture ......................................................................................... 23
2.3.1 DSP Coprocessor 0 (CP0).....................................................................................23
2.3.1.1 Multiply With Internal Accumulate Format .............................................24
2.3.1.2 Internal Accumulator Access Format ..................................................... 27
2.3.2 New Page Attributes .............................................................................................. 29
2.3.3 Additions to CP15 Functionality ............................................................................. 31
2.3.4 Event Architecture .................................................................................................32
2.3.4.1 Exception Summary ............................................................................... 32
2.3.4.2 Event Priority..........................................................................................32
2.3.4.3 Prefetch Aborts ...................................................................................... 33
2.3.4.4 Data Aborts ............................................................................................34
2.3.4.5 Events from Preload Instructions ...........................................................35
2.3.4.6 Debug Events ........................................................................................ 36
2.3
3
Memory Management....................................................................................................................37
3.1
3.2
Overview ............................................................................................................................. 37
Architecture Model.............................................................................................................. 38
3.2.1 Version 4 vs. Version 5 ..........................................................................................38
3.2.2 Memory Attributes.................................................................................................. 38
3.2.2.1 Page (P) Attribute Bit ............................................................................. 38
Developer’s Manual
January, 2004
3
Intel XScale® Core Developer’s Manual
Contents
3.3
3.4
3.2.2.2 Cacheable (C), Bufferable (B), and eXtension (X) Bits.......................... 38
3.2.2.3 Instruction Cache ................................................................................... 38
3.2.2.4 Data Cache and Write Buffer ................................................................. 39
3.2.2.5 Details on Data Cache and Write Buffer Behavior................................. 40
3.2.2.6 Memory Operation Ordering .................................................................. 40
3.2.3 Exceptions ............................................................................................................. 40
Interaction of the MMU, Instruction Cache, and Data Cache ............................................. 41
Control ................................................................................................................................ 42
3.4.1 Invalidate (Flush) Operation .................................................................................. 42
3.4.2 Enabling/Disabling ................................................................................................. 42
3.4.3 Locking Entries ...................................................................................................... 43
3.4.4 Round-Robin Replacement Algorithm ................................................................... 45
4
Instruction Cache........................................................................................................................... 47
4.1
4.2
Overview............................................................................................................................. 47
Operation ............................................................................................................................ 48
4.2.1 Operation When Instruction Cache is Enabled...................................................... 48
4.2.2 Operation When The Instruction Cache Is Disabled.............................................. 48
4.2.3 Fetch Policy ........................................................................................................... 49
4.2.4 Round-Robin Replacement Algorithm ................................................................... 49
4.2.5 Parity Protection .................................................................................................... 50
4.2.6 Instruction Fetch Latency....................................................................................... 51
4.2.7 Instruction Cache Coherency ................................................................................ 51
Instruction Cache Control ................................................................................................... 52
4.3.1 Instruction Cache State at RESET ........................................................................ 52
4.3.2 Enabling/Disabling ................................................................................................. 52
4.3.3 Invalidating the Instruction Cache.......................................................................... 53
4.3.4 Locking Instructions in the Instruction Cache ........................................................ 54
4.3.5 Unlocking Instructions in the Instruction Cache..................................................... 55
4.3
5
Branch Target Buffer ..................................................................................................................... 57
5.1
Branch Target Buffer (BTB) Operation ............................................................................... 57
5.1.1 Reset ..................................................................................................................... 58
5.1.2 Update Policy......................................................................................................... 58
BTB Control ........................................................................................................................ 59
5.2.1 Disabling/Enabling ................................................................................................. 59
5.2.2 Invalidation............................................................................................................. 59
5.2
6
Data Cache.................................................................................................................................... 61
6.1
Overviews ........................................................................................................................... 61
6.1.1 Data Cache Overview............................................................................................ 61
6.1.2 Mini-Data Cache Overview .................................................................................... 63
6.1.3 Write Buffer and Fill Buffer Overview..................................................................... 64
Data Cache and Mini-Data Cache Operation ..................................................................... 65
6.2.1 Operation When Caching is Enabled..................................................................... 65
6.2.2 Operation When Data Caching is Disabled ........................................................... 65
6.2.3 Cache Policies ....................................................................................................... 65
6.2.3.1 Cacheability ........................................................................................... 65
6.2.3.2 Read Miss Policy ................................................................................... 66
6.2.3.3 Write Miss Policy.................................................................................... 67
6.2.3.4 Write-Back Versus Write-Through ......................................................... 67
6.2
4
January, 2004
Developer’s Manual
Intel XScale® Core Developer’s Manual
Contents
6.3
6.4
6.5
7
6.2.4 Round-Robin Replacement Algorithm ................................................................... 68
6.2.5 Parity Protection .................................................................................................... 68
6.2.6 Atomic Accesses ................................................................................................... 68
Data Cache and Mini-Data Cache Control .........................................................................69
6.3.1 Data Memory State After Reset ............................................................................. 69
6.3.2 Enabling/Disabling .................................................................................................69
6.3.3 Invalidate and Clean Operations ........................................................................... 69
6.3.3.1 Global Clean and Invalidate Operation .................................................. 70
Re-configuring the Data Cache as Data RAM .................................................................... 71
Write Buffer/Fill Buffer Operation and Control .................................................................... 75
Configuration ................................................................................................................................. 77
7.1
7.2
Overview ............................................................................................................................. 77
CP15 Registers................................................................................................................... 80
7.2.1 Register 0: ID & Cache Type Registers ................................................................. 81
7.2.2 Register 1: Control & Auxiliary Control Registers .................................................. 83
7.2.3 Register 2: Translation Table Base Register ......................................................... 85
7.2.4 Register 3: Domain Access Control Register......................................................... 85
7.2.5 Register 4: Reserved ............................................................................................. 85
7.2.6 Register 5: Fault Status Register ........................................................................... 86
7.2.7 Register 6: Fault address Register ........................................................................ 86
7.2.8 Register 7: Cache Functions ................................................................................. 87
7.2.9 Register 8: TLB Operations ................................................................................... 89
7.2.10 Register 9: Cache Lock Down ............................................................................... 90
7.2.11 Register 10: TLB Lock Down ................................................................................. 91
7.2.12 Register 11-12: Reserved ...................................................................................... 91
7.2.13 Register 13: Process ID ......................................................................................... 91
7.2.13.1 The PID Register Affect On Addresses ................................................. 92
7.2.14 Register 14: Breakpoint Registers .........................................................................93
7.2.15 Register 15: Coprocessor Access Register ...........................................................94
CP14 Registers................................................................................................................... 96
7.3.1 Performance Monitoring Registers ........................................................................ 96
7.3.1.1 XSC1 Performance Monitoring Registers .............................................. 96
7.3.1.2 XSC2 Performance Monitoring Registers .............................................. 97
7.3.2 Clock and Power Management Registers.............................................................. 98
7.3.3 Software Debug Registers .....................................................................................99
7.3
8
Performance Monitoring .............................................................................................................. 101
8.1
8.2
Overview ........................................................................................................................... 101
XSC1 Register Description (2 counter variant) ................................................................. 102
8.2.1 Clock Counter (CCNT; CP14 - Register 1) .......................................................... 102
8.2.2 Performance Count Registers (PMN0 - PMN1;
CP14 - Register 2 and 3, Respectively)............................................................... 103
8.2.3 Extending Count Duration Beyond 32 Bits .......................................................... 103
8.2.4 Performance Monitor Control Register (PMNC) ..................................................103
8.2.4.1 Managing PMNC.................................................................................. 105
XSC2 Register Description (4 counter variant) ................................................................. 106
8.3.1 Clock Counter (CCNT)......................................................................................... 106
8.3.2 Performance Count Registers (PMN0 - PMN3) ................................................... 107
8.3.3 Performance Monitor Control Register (PMNC) ..................................................108
8.3.4 Interrupt Enable Register (INTEN).......................................................................109
8.3
Developer’s Manual
January, 2004
5

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin