SLA9000F.PDF

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PF841-02
SLA9000F Series
qHigh
speed, high integration gate array.
qNumber
of gates mounted: 2.7K to 44K gates.
s
DESCRIPTION
The SLA9000F series is a SOG type CMOS gate which has realized high speed, high integration and high
driving capability. This series is offered with 2,784 to 44,070 gates to ensure an optimum application for any mid
size high speed systems.
This series is designed to operate on both 5 V and 3 V systems to correspond to increasing low-voltage oriented
applications. Simplified level shifter cell is available on this series. And, the
µA
order low noise output cell of the
series has made it suitable for small size, handy equipments and many other applications.
s
FEATURES
q
Super-high density (adopting 1.0µm silicon gate CMOS with 2-metal layer)
q
High-speed operation (operation delay of internal gate = 0.3ns at 5.0V, 2-input Power NAND standard)
q
Simplified level shifter cells available
q
Output drivability (I
OL
= 100µ, 2, 6, 12, 24 mA when 5.0V, I
OL
= 100µ, 2, 4, 8, 12mA when 3.3V)
q
On-chip RAM available
q
Low noise output cells available
s
PRODUCT LINEUP
Master
Total BCs (Raw Gates)
Usable Bcs
Number of PADs
Internal Gates
Propagation
Input Buffers
Delay
Output Buffers
I/O Level
Input Mode
Output Mode
SLA902F
2,784
1,809
80
SLA904F
4,392
2,854
SLA907F
7,872
4,723
SLA909F
9,540
5,724
SLA913F
13,144
7,229
SLA919F
19,350
10,642
SLA927F
27,234
13,617
SLA944F
44,070
22,035
256
100
128
144
160
184
208
tpd = 0.30ns (standard at 5.0V), tpd = 0.43ns (standard at 3.3V)
tpd = 0.91ns (standard at 5.0V), tpd = 1.08ns (standard at 3.3V)
tpd = 3.5ns (standard at 5.0V), tpd = 4.2ns (standard at 3.3V) CL = 50pF
TTL, CMOS
TTL, CMOS, Pull-up/Pull-down, Schmitt, 3.0/3.3/5.0V Level interface
Normal, Open drain, 3-state, Bi-directional, 3.0/3.3/5.0V Level interface
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SLA9000F
Series
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability
of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and,
further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical
products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no
representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products
under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the
Ministry of International Trade and Industry or other approval from another government agency.
All product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
©Seiko Epson Corporation 1998 All rights reserved.
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I
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II
(Asia)
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http://www.epson.co.jp
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